Abstract: A multi-rate transmission system (10) includes a receive section (12) and a transmit section (14). The receive section includes a receiver (16), a clock recovery unit (18), and a serial to parallel converter (20) all operating at a first clock rate (M). The receiver (16) also has a frame recovery unit (22) that operates at any of a plurality of clock rates, including the first clock rate (M) and a second clock rate (M/n). When the frame recovery unit operates at the first clock rate (M), frame information received by the receiver section (12) has unique bits occupying each bit position associated with each clock pulse of the first clock rate (M). When the frame recovery unit (22) operates at the second clock rate (M/n), each unique bit of the frame information occupies a number of bit positions according to a ratio of the first clock rate (M) to the second clock rate (M/n). Similar operation occurs with respect to a frame formatter (30) in the transmit section (14) of the multi-rate transmission system (10).

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Abstract: An encoder for encoding binary data bits supplied by a data source into pulse amplitude modulated multilevel symbols. The encoder includes a bit stuffer for receiving the data bits from the data source at a first data bit rate, which at most equals a maximum data bit rate. The bit stuffer then adds descriptive bits to the data bits at a descriptive bit rate, which at most equals a maximum descriptive bit rate. The encoder also includes a multilevel pulse amplitude modulator for receiving the data and descriptive bits from the bit stuffer and for converting the data and descriptive bits into pulse amplitude modulated multilevel symbols. When these multilevel PAM symbols are transmitted, they have a spectral energy characteristic which is below a predetermined low level threshold at a predetermined baseband bandwidth frequency. In addition, these multilevel PAM symbols have a symbol rate (i.e.

Abstract: A data recovery technique for jitter tolerant peak detected channels. The number of consecutive zeros between ones are reproduced in a run-length coded, peak detected channel. The interval (time, distance) is measured between peaks of a run-length encoded digital data signal wherein peaks represent ones and absence of peaks represent zeros. A look-up-table is provided having entries for all possible intervals between peaks for the run-length code used and corresponding entries for the number of zeros between ones. The measured interval is applied to the look-up-table to produce a string of zero bits between one bits.

Abstract: A system for communicating digital data comprises a splitting device (38) for separating an input digital data word, which may be provided by a speech coding arrangement (34,36), into most significant bits and less significant bits. The most significant bit(s) of the digital data word are encoded (40) using a robust signalling alphabet and less significant bit(s) are encoded (42,44) using progressively less robust signalling alphabets. All of the symbols resulting from the encoding are combined (46) and transmitted (48). On reception (50) the received signal is split (52) and demodulated (54,56,58) to provide respective portions of a received data word to a combining means (60). Where the data word was originally provided by speech coding arrangement the received data word may be provided to a resynthesising arrangement (62,64). The signalling alphabets may comprise 2-level modulation, 3,4 and 8-level modulation and/or phase modulation of various degrees.

Abstract: A communications system (30) includes a transceiver (42) for transmitting data from a plurality of bins. Specifically, the BER of the bins is substantially equalized by allocating data by determining a projected margin. The projected margin is calculated for each bin by subtracting a reference signal-to-noise value from an estimated bin signal-to-noise value. The reference signal-to-noise value is predetermined by theoretical calculation or empirical data and stored in a look-up table. Bits are allocated to the bin having the maximum projected margin. This provides the best BER without changing the transmit power.

Abstract: A binary data communication system includes a transmitter unit coupled to a receiver unit via a communications link. The transmitter sends a message signal packet to the receiver. The packet includes data arranged according to mixed protocols. The receiver unit includes a program for detecting both protocols, and for converting data from one protocol (or format) into the other format.

Abstract: In a serial data transmission apparatus connected to a data transmission bus, an edge detector detects an edge in a signal at the data transmission bus. An edge interrupt operation is carried out to operate a timer in response to the edge. The edge interrupt operation is stopped when the timer is being operated. A timer interrupt operation carries out a fetching operation of a bit data on the data transmission bus in a receiving mode or a transmitting operation of a bit data to the data transmission bus in a transmitting mode, in response to the timer means whose content reaches a predetermined value.

Abstract: A specially designed external reset circuit for a modem in a computer system includes an external reset switch provided on the computer system accessible to a user and operable to generate a manual reset signal in response to the user's manipulation of said external reset switch. A signal stability circuit is connected to the external reset switch, for stabilizing the manual reset signal and preventing occurrence of a sudden surge of voltage when the external reset switch is turned on and turned off. A signal combination circuit includes a first input terminal coupled to receive occurrence of the manual reset signal and a second input terminal coupled to receive occurrence of a computer reset signal generated from the computer system, for logically combining occurrence of the manual reset signal and the computer reset signal to generate a modem reset signal.

Abstract: A single clock cycle adaptive data compressor/decompressor with a string reversal mechanism is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The LZW data compression algorithm has been improved for use in this data compressor. The compressor builds a string table as the data is received. Each string within the table is made up of the address within the table of the longest previously seen matching string and the one character that makes this string different. This data compressor/decompressor utilizes a content addressable memory to store the string table. This content addressable memory allows the compressor to store the current symbol string in a table while that same string table is simultaneously searched for the current string. During decompression the characters within a symbol string are output in reverse of the order in which they were input.

Abstract: A method and apparatus for negotiating service configuration in a digital communication system is disclosed. In an exemplary embodiment the service negotiation system is implemented in a wireless spread spectrum communication system. The service configuration comprises data rates, frame formats and types of services. Types of service may include speech encoding, facsimile or digital data services. Further described herein is a digital transmitter and receiver using the service negotiation system to provide service configuration mutually acceptable at both ends of a communication link.

Abstract: A communications intercept device that includes an analog-to-digital converter for digitizing an analog wideband input signal, a first memory for storing the digitized wideband signal, a first digital drop receiver in a first tier for selecting signals stored in the first memory, a controller for controlling which signals are selected, a second memory for storing the signals selected by the first digital drop receiver, and a second digital drop receiver in a second tier for selecting signals stored in the second memory under control of the controller.

Abstract: Methods and apparatus for providing high speed inter-computer data transmission using multiple low speed communication links. At the transmitting site, a high speed data stream is split into multiple low speed data stream and multiplexed onto to the low speed links. The receiver demultiplexes, buffers, and synchronizes the multiple low speed data streams to recreate the high speed data stream.

Abstract: A memory is coupled to a processor in the computer system to implement a modem with simultaneous voice and data capabilities. The modem comprises a communication port to couple the computer system to a phone line, and software in the memory. The memory comprises a first software component which, when executed on the processor, provides a data input to the physical communication port, and a second software component which, when executed on the processor, provides a voice input to the physical communication port. The first and second software components cooperate to enable simultaneous voice and data communication through the physical communication port.

Abstract: A system and method for transmitting data within a computer system is disclosed. The computer system includes a computer (12), a host device (14), a satellite device (16) and an interface (18). The interface (18) comprises a single conductor (28) which permits bi-directional communication between the host device (14) and the satellite device (16).

Abstract: A data transmission method entails differentially transmitting low-pass filtered first outgoing data to and through an isolation transformer at a first data rate. Second outgoing data is differentially transmitted to and through the transformer in the same direction as the first outgoing data but at a second data rate different from, typically greater than, the first data rate. The so-transmitted first and second outgoing data is coupled from the transformer to a communication cable during different time intervals. A related data reception method involves coupling incoming data from a communication cable to and through the isolation transformer and providing the so-coupled incoming data differentially along data transfer paths that extend from the transformer to and through where data moving at the first data rate is received to where data moving at the second data rate is received such that the data transfer paths have a largely constant characteristic impedance.

Abstract: A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

Abstract: A receiver and a method for adding a sequence, embedded in a digital sequence of data together with another sequence, separate of the other sequence to at least a part of the digital sequence of data. An example of such a sequence is the Program Associated Data (PAD) in a DAB digital sequence of data, this PAD being embedded in audio frames together with audio data. The DAB digital sequence of data is converted into a sequence according to the IEC958 format, wherein the retrieved PAD is inserted into the User Data channel in the IEC958 frames. This allows an easy retrieval of the PAD from the digital sequence of data, without the need for analyzing audio frames and retrieving the PAD therefrom.

Abstract: A method of bypassing vocoders in a digital mobile communication system, comprising the step of appending bypass mode data to data transmitted from a plurality of mobile stations, the bypass mode data instructing the vocoders not to perform encoding/decoding operations, and the step of transmitting the resultant data. According to the present invention, the unnecessary encoding/decoding operations are omitted for a mobile to mobile communication. Therefore, the present invention has the effect of removing the delay time and enhancing the voice quality.

Abstract: In the present invention, a line driver circuit enables multiple timing signal generators to simultaneously deliver a timing signal to a load. The multiple or redundant timing signal generators each having a line driver circuit, provide an uninterrupted timing signal that is independent of failures of individual timing signal generators. The multiple timing signal generators share the task of providing the timing signal, i.e. power, to the load. In the event of a failure of one of the timing signal generators, the task of providing power to the load shifts to other of the multiple signal generators, maintaining an uninterrupted timing signal, undisturbed in amplitude, phase and pulse shape. The line driver of each timing signal generator has a drive capability to exceed that required for the timing signal. A voltage clamp regulates the amplitude of the timing signal when the timing signal generators are simultaneously functioning.

Abstract: A communications system employing a telestation that uses a computer to provide command and data handling, a GPS receiver to provide position, time, and attitude information, and a transceiver to provide two-way wireless digital communications. The computer is coupled to an instrument, measuring device, or payload, and is controlled to relay data generated thereby to a user. Commands and data are uplinked and downlinked to the telestation by way of a satellite network, such as a Globalstar network. The telestation provides a user with real-time command and control of globally distributed instruments. This capability may be used terrestrially for gathering information (e.g., science, environmental, etc.) in remote or inhospitable locations, or where logistical support is inadequate. An in-orbit version may be used for spacecraft or satellite instruments 15, allowing investigators instant access to the instruments during all phases of a mission.

Abstract: A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated remotely using a clock having a frequency that may be different than the frequency of the clock in the receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle.

Abstract: An apparatus and method are provided for a data communications device, such as a modem (100,101), software modem, or facsimile machine, to detect and discriminate various amplitude modulated signals, such as an ANS signal of the ITU V.25 protocol and an ANSam signal of the ITU V.8 protocol. The apparatus and method embodiments first determine the presence of a first frequency component in a received signal, such as the 2100 Hz component of ANS and ANSam signals (205). The received signal is then demodulated (215) and low pass filtered (220), followed by removing any resulting direct current component (225) to form an inclusive signal. A second frequency component, such as the frequency of the 15 Hz amplitude modulating component of an ANSam signal, is removed from the inclusive signal (235), and its resulting magnitude is determined, as a filtered signal magnitude (240). The filtered signal magnitude is subtracted from the magnitude of the inclusive signal (230) to form a discrimination value (245).

Abstract: A data-transmitting apparatus contains first and second transmitters, a transmit transformer, and a connecting unit for coupling the transformer to an outgoing twisted-pair cable. The first transmitter filters data to produce outgoing data transmitted to the transformer at a first data rate. The second transmitter transmits outgoing data to the transformer at a different, typically greater, second data rate. A data-receiving apparatus contains first and second receivers, a receive transformer, and a connecting unit for coupling an incoming twisted-pair cable to the receive transformer. The first and second receivers receive incoming data from the secondary winding respectively at the first and second data rates. Incoming data is typically provided along data transfer paths that extend from the receive transformer in a daisy chain manner to the receivers. Data moving at either data rate can be transmitted and received without the need for hot switching in the data paths.

Abstract: A reordering device 1.sub.-- 1 rearranges the segments of each block of time series data comprised of a plurality of blocks in block units. A selecting device 2.sub.-- 1 selects from among a plurality of time series data S1.sub.-- 1 to 1.sub.-- 4 rearranged by the reordering device 1 by switching in accordance with the speed and transmits the corresponding segments of the selected time series data sequentially to the reordering device 3.sub.-- 1 etc. as the streams S2.sub.-- 1 etc. The repeat reordering device 3.sub.-- 1 rearranges the segments contained in the stream S2.sub.-- 1 in units of blocks so as to restore the original order and transmits this rearranged time series data.

Abstract: A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable digital oscillator, a phase comparator, a programmable counter and delay control logic. The programmable digital oscillator is a ring connected programmable delay line and inverter which together generate an output clock signal having a frequency which depends upon the time delay of the programmable delay line. The phase comparator compares the phase of the output clock signal to that of a reference clock signal and generates a phase error signal which represents the phase difference between such signals. The programmable counter, programmed and reprogrammed with the arrival of every reference clock signal pulse, counts the output clock signal pulses to generate a count signal.

Abstract: The invention concerns a data transmission circuit, for use on a mains electricity network, that includes a modulator/ demodulator circuit that supplies a first signal, which indicates if the network is occupied, that is based upon a comparison between the level of a received signal and a predetermined threshold value and circuitry for switching a modem into its receive mode or its transmit mode, including a digital circuit that supplies a second signal that indicates the occupation of the network based on the identification of a predetermined data sequence that is present within each transmission stream before a data message and circuitry for allowing the modem to switch to its transmit mode when the occupation signals indicate an absence of a transmission.

Abstract: A network hub or a network switch including a housing which holds all elements of the network hub; a trunk interface control unit which is the control center of the network hub for controlling the operation of the other units of the network hub; a power supply unit connected to the trunk interface control unit to provide the network hub with the necessary operating power; a plurality of modular jacks adapted for receiving network lines for data input and output; a plurality of data handling units respectively connected between the trunk interface control unit and the modular jacks for handling input data and output data; a functional operand unit connected to the trunk interface control unit for calculating network line connection condition, network line utilization rate, data collision rate and network line inspection condition; a voice function control unit connected to the trunk interface control unit for controlling the functional operand unit to output its computed result, and a LED controller controlled

Abstract: A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.

Abstract: A method of transmitting digital signals which allows transmission of signals at a different transmission speed from that of composite serial digital signals, without any changes in the internal configurations of transmitting systems based on time division multiplexing, and a transmitter and a receiver used therefor. Dummy data is added to component serial digital signals inputted through an input terminal 10, with a decoder 21, a dummy data add circuit 22 and a 35/33 multiply circuit 23, to convert them into redundant component parallel digital signals of a sampling frequency twice the frequency of the composite parallel digital signals. The signals are converted into two series of pseudo composite serial signals with an encoder 24, a ten-fold multiply circuit 25 and a switching circuit 26, and then sent to a time division multiplexer for a plurality of composite serial digital signals.

Abstract: A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host.

Abstract: An infra-interface section 15 in a radio modem has a function of radio interfacing with a plurality of radio lines. An interface section 16, conforming to the PCMCIA standard, connects with a data terminal unit to which this radio modem is to be connected. A memory section 17 stores information transmitted or received by the infra-interface section 15. A display section 14 displays the stored transmit/receive information. A control section 18 controls all these sections. By having transmit/receive information, when data are transmitted or received via radio lines, stored into the memory section 17 and then displayed in the display section 14, the user of the terminal is enabled to recognize, by locking at the display section, the plurality of conditions of transmission/reception on a real time basis without confusing them with one another.

Abstract: A transmitter in a process control loop includes a sensor for sensing a process variable. An analog-to-digital converter coupled to the sensor provides a digitized process variable at various sample times. An interface couples the transmitter to the control loop and is used for communicating information and receiving power over the control loop. The transmitter includes a clock and a memory. A microprocessor coupled to the clock and the memory stores digitized process variables and clock information in the memory. The storage is such that the sample time of a stored digitized process variable can be determined.

Abstract: A method of cellular communication among a subscriber unit, a base station and a switch controller is provided which comprises the steps of digitally encoding speech signals at the subscriber unit; generating radio forward error correction (FEC) at the subscriber unit to protect the encoded speech signals during transmission; transmitting the encoded speech signals together with the radio FEC by radio from the subscriber unit to the base station; error correcting the transmitted encoded speech signals at the base station using the radio FEC; generating wire FEC to protect the encoded speech signals during transmission; transmitting the encoded speech signals together with the wire FEC from the base station to the controller; error correcting the transmitted encoded speech signals at the controller using the wire FEC; and decoding the digitally encoded speech signals at the controller.

Abstract: A portable, integrated transmission system and portable, integrated receiving system; system, includes a transmit interface unit, a transmit signal processing unit, a transmit signal converting unit and a microwave transmitting unit all a first location. The system further includes a microwave receiving unit, a receive signal converting unit and a second signal processing unit. A satellite communications link can be established between the portable, integrated transmission system located anywhere in the world and the portable integrated receiving system located anywhere in the world. The satellite link makes it possible to transmit information such as an audio/video signal of broadcast quality or file information via satellite from anywhere in the world to anywhere in the world (except the polar caps) in real time.

Abstract: An interface for connecting data-terminal-equipment (DTE) to a range of data-communication-equipment (DCE) using a multiplicity of interface standards is provided. The interface includes a DTE panel connector and a plurality of line drivers and receivers and associated electronics to select predetermined ones of the plurality of receivers and drivers for use the DTE when cables having a predetermined configuration, corresponding to the supported interface standards, are attached. The cables connect the appropriate drivers and receivers of the DTE with the corresponding receivers and drivers, respectively, of the DCE. Additionally the cables also contain termination devices and a selection mechanism to select which drivers and receivers are to be used by the DTE to communicate with the receivers and drivers respectively, being used by the DCE.

Abstract: The present method (200,300, 400) and device (500, 600, 700) modify phase two of the format set forth in the V.34 Recommendation of the International Telecommunication Union-Telecommunication Standardization Sector to prevent premature disconnection of calls between a call modem and an answer modem. The method and device efficiently ensure connection of the call for high speed data transmission over voiceband channels, by modification of one of: a phase preliminary to phase one and phase two. One implementation, in the answer modem, includes transmitting a signal having first information, followed by a Signal S comprising of aguard tone and a signal S1, wherein an energy of a predetermined guard tone is greater than an energy of a predetermined range of frequencies of the Signal S1; and continuing transmitting and receiving in accordance with the modified V.34 operation.

Abstract: parallel interface is provided between a standard parallel port of a computer system and a modem so as to increase the data transfer rate between the two systems without modifying the hardware of the computer system and independently of the application program running on the computer system.

Abstract: Disclosed are digital data receivers, methods and circuitry for differentiating between signals and data packets of varying physical layer protocols and frequencies transferred over a digital burst mode communications system, such as a packet-based LAN. Transitions in a received input signal to a squelch circuit start a counter which asserts one or more signals at various predetermined times from the transition. The absence or presence of the signal when the next transition in the input signal occurs indicates whether the input signal is less than or greater than a frequency associated with a particular predetermined time interval. When a predetermined number of transitions meeting a particular frequency requirement are received, the input signal is determined to be received at a particular frequency.

Abstract: Serial high speed interconnect devices are integrated with semiconductor devices for simple and reliable communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface circuit technology that may be easily implemented on a semiconductor die in conjunction with the main circuits.

Abstract: A method and apparatus is provided allowing a dual-speed network adapter to connect to the same physical connector without the use of mechanical or electro-mechanical switches. On the transmit path, the invention uses a differential amplifier buffer (130) to selectively couple a high speed transmit paths to the network, with the differential amplifier connected to the same output impedance as one of the two driver circuits. On the receive path, the invention allows data to be received in parallel by two receiver circuits, with one circuit isolated from the other with a pair of very high input impedance emitter/followers (40, 50).

Abstract: Disclosed is a data transmission system comprising a first device having first clock generator for generating a first clock signal for data exchange with a second device, second clock generator for generating a second clock signal for resetting the second device to be operable, and clock supplying unit for supplying the first and second clock signals to the second device, and the second device for performing data exchange with the first device in response to the first clock, the second device being reset by the second clock. It is thus possible to ensure data exchange using existing hardware such as a UART, while supplying a reset clock whose frequency will not be a multiple of 1200 bps even by frequency division by 2.sup.n, to the IC card. This data transmission system will therefore cope with both the demand for the ISO standardization and the use of existing hardware.

Abstract: A method of converting GMSK modulated signals arriving at an integer multiple of the IS-54 standard sampling (or symbol) rate (24.3 KHz) to GMSK modulated signals at an integer multiple of the CDPD standard sampling rate (19.2 KHz). In the preferred embodiment, the GMSK signals arrive as serial in-phase (I) samples and quadrature-phase (Q) samples at the IS-54 sampling rate. The method of the present invention combines into one calculation the following operations 1) time-alignment of the serial I and Q samples into IQ pairs, 2) conversion of the time-aligned IQ pairs to the CDPD sampling rate of 4.times.19.2 KHz, and 3) sign correction of each time-aligned IQ pair. Because of the periodic nature of certain variables in the above calculation, efficiency is further achieved with the present invention by storing tables containing the possible values of these variables, then using pointers to access the stored values as needed, thereby saving considerable processing power and time.

Abstract: Improved apparatus for a radio communication system having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which communicate with one or two host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. A network controller provides selective interface means to be employed between the host computers and the base transceivers whereby low data rate base transceivers may be utilized with the network controller while spread spectrum or high data rate networked base transceivers may be also utilized. The network controller may allow selection of interface means for three of its ports from its front panel with use of three input keys. The network controller is entirely external to the host computer or computers, and can couple to a variety of commonly encountered host ports.

Abstract: An electronic receiver for a digital communication system which eliminates cumulative jitter is comprised of an input circuit which receives a continuous series of bits, on an input terminal, at a receiver input bit rate. This series of bits consists of data bits in spaced apart data blocks, with respective headers that have a variable length and fill the space between the data blocks. Also, the receiver includes an output circuit, which is coupled to the input circuit. This output circuit sends selected bits from the data blocks, but not from the headers, to an output port at a receiver output bit rate which is slower than the receiver input bit rate. Further, the output circuit includes a closed loop feedback control circuit, which selects the receiver output bit rate, such that it is substantially constant and such that the selected bits from the data blocks occur on the output port as a continuous bit stream.

Abstract: An image communication apparatus for storing a plurality of image data to be transmitted, respectively, in correspondence with identification data of destination stations, and sequentially transmitting the stored image data to corresponding destination stations, includes a first determining unit for determining validity of a communication speed, a second determining unit for determining whether additional data to be transmitted to a given destination station are present at the time of transmission of image data to the given destination station, and a controller for transmitting all the additional data to be transmitted to the given destination station without disconnecting a line when the second determining means determines that the additional data to be transmitted to the given destination station are present and the first determining means determines that a valid communication speed is currently used.

Abstract: In a simultaneous voice and data communications system comprising two modems, an autorate feature is implemented in one illustrative method by adding a silence detector to the receiver circuitry of at least one of the modems in such a way that noise statistics for the communications channel are only accumulated during intervals of silence. If the resulting noise statistics exceed a predetermined threshold, i.e., the communications channel is too noisy, the receiving modem negotiates a lower data rate with the transmitting modem. In another illustrative method, the transmitting modem provides a signal, which represents an interval of silence, to the receiving modem. Upon receipt of the signal, the receiving modem accumulates error statistics in order to determine if the communications channel is too noisy.

Abstract: A clock control unit is provided that controls the gating of a clock signal received by an internal baud generator of a universal asynchronous receiver/transmitter (UART) circuit during an active mode. The clock control unit monitors the UART circuit to determine whether the UART is currently idle. If the clock control unit determines that the UART is idle, the clock signal is gated by a synchronous clock gate circuit. Accordingly, the clock signal is not provided to the baud generator, and a corresponding baud rate signal that normally clocks the receiver state machine of the UART is not generated. Power consumption of the UART is thereby significantly reduced. When a certain predetermined system activity is thereafter detected by the clock control unit that indicates a need for activation of the UART, the clock control unit asserts a clock enable signal that causes the synchronous clock gate circuit to pass the clock signal to an input of the baud generator.

Abstract: A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node.

Abstract: A downward compatible full-duplex ethernet transceiver associated with either the hub or the remote node in an ethernet local area network (LAN) includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over a link of the LAN and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the link of the LAN. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of from about 2 to about 7 microseconds.