Abstract: In a data communication system, a transmitter of an ADSL modem uses a PRBS generator to generate a plurality of ADSL signals. The transmitter computes the Peak to Average (e.g., root-mean-square) (“PAR”) ratio of each of the ADSL signals generated. The ADSL signal having the lowest PAR is determined, and the corresponding state of the PRBS generator is noted. The signal having the lowest PAR, or at least the corresponding state of the PRBS generator, is then used to generate a Q-mode signal.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: This invention aims to make it possible to realize data communication having excellent communication throughput and good quality even if the communication state fluctuates. According to the present invention, by sequentially adjusting the transmission speed of data that is to be sent to the portable radio terminal 22 on the basis of momentary real transmission speed in the communication channel 6 that has been fed back from the portable radio terminal 22, and hereby controlling the data communication speed between itself and the portable radio terminal 22, it is able to execute data transmission processing that is corresponding to changes of transmission speed in the communication channel 6, in this way, it is able to realize data communication having excellent communication throughput and good quality even if the communication state fluctuates.

Abstract: A method and apparatus for transmitting digital data in a cellular environment. Adjacent cells of the cellular system are prevented from simultaneously transmitting data. Because the noise from transmissions of adjacent cells is a primary source of interference, the transmission rate of power limited base stations can be dramatically increased when the noise from adjacent cells is eliminated. The transmissions to each subscriber station are made at a fixed transmission power level. However, the data rate of transmitted signals differs from one subscriber station to another depending the path loss differences. In a first exemplary embodiment, the data rate of transmissions to a subscriber station is determined by selecting an encoding rate for the transmitted signal while holding the symbol rate constant.

Abstract: An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit.

Abstract: A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.

Abstract: A method and circuitry for channel estimation in a cellular communication system is disclosed. Data is transmitted with variable data transmission rates as a plurality of data symbols over a sequence of time slots. Each time slot has at least a proportion containing data symbols, the proportion being dependent on the data transmission rate. An estimate of the transmission rate is determined and is used in channel estimation so that the channel estimation is based on the proportion of received data symbols.

Abstract: A data stream (DS) comprises a time multiplex of coded data (D) and control data (C). The data stream (DS) may be, for example, of the MPEG type representing a sequence of pictures. The coded data (D) is transcoded (T) so as to obtain transcoded data (DT) which differs in size from the coded data (D). The control data (C) is adapted for the transcoded data (DT) so as to obtain adapted control data (CA) which does not substantially differ in size from the control data (C). The transcoded data (DT) and the adapted control data (CA) are written into a transcoder output buffer (TOB) and read from the transcoder output buffer (TOB) so as to obtain a transcoded data stream (DST). This allows an efficient use of a transmission channel via which the transcoded data stream (DST) is to be transmitted and, consequently, it allows a satisfactory transcoding quality.

Abstract: A data signal attenuator is constructed to include an optocoupler, a biasing source for powering the optocoupler and restoring the amplitude of an originally transmitted signal, and a connector for connecting the attenuator to the exterior of a receiving device. When connected to the receiver, the attenuator electrically connects a single-ended data transmission line to the receiving device. The external connection of the attenuator to the receiving device thus enables existing receivers to have the benefits of an optocoupler based attenuator without the necessity of redesign.

Abstract: A reverse data rate controlling method in a mobile communication system for transmission of packet data is provided. In an embodiment of the present invention, an RRL (Reverse Rate Limit) message includes an ignore RAB (Reverse Activity Bit) field to ensure a predetermined data rate for a particular access terminal (AT). In another embodiment of the present invention, an access probability is set for each data rate in the RRL message. Upon receipt of an RAB, an AT compares a random number with the access probability for its data rate and increases or decreases the data rate according to the comparison result.

Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested.

Abstract: Process for interconnecting between data processing or data communication modules (A and B) by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. It consists, on transmission and on reception, of performing an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and of digitally synchronizing the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: A method for adaptive-rate communication includes setting a first target signal margin with respect to an actual noise level and a second target signal margin with respect to a predetermined noise level. The actual noise level is measured at a receiver on a communication channel between a transmitter and the receiver. A transmission rate is selected at which to transmit a signal on the channel such that for the selected transmission rate, a first signal-to-noise ratio (SNR) of the signal relative to the measured actual noise level is greater than a baseline SNR level by at least the first target signal margin, and a second SNR of the signal relative to the predetermined noise level is greater than the baseline SNR by at least the second target signal margin.

Abstract: An analog front end (AFE) circuit used in a high-speed communications system is presented that includes multiple stages each including a bandpass filter, base band modulator, low pass filter and Sigma-Delta modulator. Each stage processes a fractional portion of the total frequency of a wide bandwidth analog signal. The number of such AFE stages is configurable in parallel to process the entire bandwidth of the received signal. The AFEs can be incorporated in a single integrated circuit or similar suitable manner so as to be modular, and easily replaceable/upgradeable. To achieve minimum quantization noise and reduce manufacturing costs, the Sigma-Delta modulators in each AFE are made to have identical characteristics. Because the wideband signal is broken down into smaller frequency portions, the sampling rate, and thus the complexity and cost associated with the AFEs, is reduced significantly.

Abstract: A method of parallel data rate setting for first and second modem pools, each modem pool including a plurality of modems, where each modem in one of the modem pools is paired with a corresponding modem in the other of the modem pools, including setting substantially in parallel each of the modem pairs to an initial data rate, for each of the modem pairs, performing the following steps one or more times until a termination condition is met: if the modem pair is synchronized within a synchronization time period, increasing the modem pair's data rate, if the modem pair is not synchronized within the synchronization time period, decreasing the modem pair's data rate, and setting each of the modem pairs to the highest data rate at which the modem pair achieved synchronization.

Abstract: A code division multiple access (CDMA) is a type of spread-spectrum communication system having a plurality of subscriber units and at least one base station. In order for a first subscriber unit to communicate with a second subscriber unit, a transmitter unit of the first subscriber unit imprints a unique code upon transmission and the second subscriber unit includes a receiver, which uses the code to decode the transmission. In addition, each transmitter with a CDMA communication system includes a stream cipher generator for enciphering the voice and data communications. Each receiver within a CDMA communication system contains an identical or similar stream cipher generator, which is used to decipher the received enciphered communication. The present invention relates to a stream cipher generator having a plurality of linear feedback shift registers to produce a stream cipher for increasing security using ciphered messages.

Abstract: A method of using a capacitively coupled interface to increase the integrity of digital signals being transmitted across the interface includes transmitting signals between a first electronic circuit and a second electronic circuit using a capacitively coupled interface, and protecting the integrity of the signals by using a protocol. The protocol preferably includes: Transmitting a signal from the first electronic circuit to the second electronic circuit on the capacitively coupled interface. After the second electronic circuit receives the signal from the first electronic circuit, transmitting a unique synchronization sequence from the second electronic circuit to the first electronic circuit on the capacitively coupled interface. Constructing a status signal that contains information concerning a status of the first electronic circuit.

Abstract: There is provided a converting processing block 3 for carrying out a processing to convert an arbitration signal into code data of 5 bits and for carrying out 4 bit/5 bit converting processing with respect to packet data to thereby carry out transmission/reception of arbitration signal and packet data as code data of 5 bits through transmitting blocks 6A, 6B and receiving blocks 7A, 7B. Thus, there is realized an interface apparatus for digital serial data which realizes extension of cable length between nodes in the digital serial data interface (e.g., IEEE 1394 high performance serial bus standard) adapted for carrying out arbitration of bus use right prior to transfer of data, thus to permit long distance transmission.

Abstract: A communications system comprising receiving and transmitting means for receiving and transmitting wireless optical signals wherein said receiving and transmitting means utilize holographic multiplexer, demultiplexer and storage technology for improved broadband where required while accommodating alternative communication modalities and protocols for maximum user benefit at lower cost.

Abstract: A digital system includes a master device, a set of slave devices, and a clock generator to generate a clock signal. A transmission channel includes a clock-to-master path extending from the clock generator, through the set of slave devices, to the master device. The transmission channel also includes a clock-from-master path extending from the master device and through the set of slave devices. The transmission channel also includes a slave-to-master path positioned between a first slave device of the set of slave devices and the master device. A master-to-slave path is positioned between the master device and the first slave device. The cumulative length of the slave-to-master path and the master-to-slave path creates a master routing phase shift between a clock signal on the clock-to-master path and a clock signal on the clock-from-master path. A first lead samples the clock signal on the slave-to-master path. A second lead samples the clock signal on the master-to-slave path.

Abstract: The present invention is a method for generating short, non-systematic, non-linear (6,4) codes that may be implemented in a 4-ARY quadrature-quadrature phase shift keying (QQPSK or Q2PSK) system over GF(16). The codewords are non-systematic in that they do not directly contain the information that is to be transmitted and six symbols are sent to represent four symbols. The present invention uses a code construction method that generates two small, hand-optimized codeword sets and combines those two codeword sets to create two larger codeword sets. The two larger codeword sets are then combined to create a codeword set that is stored in a look-up table for use at a transmission station.

Abstract: A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received.

Abstract: There is provided a method for generating a stream of N symbols by puncturing a stream of repeated symbols in a system including an encoder for generating a stream of L symbols, a repeater for repeating the stream of L symbols, and a puncturer for puncturing the stream of repeated symbols and generating a stream of N symbols, where N is larger than L.

Abstract: A system for avoiding congestion in mobile terminal communication, includes (a) a plurality of mobile stations, (b) a plurality of base stations, and (c) a base station controller connected to the base stations through a common communication line. The base station controller (a) monitors an activity ratio of a down common communication line, (b) when it is judged that the activity ratio of a down common communication line may be congested, assigns an order of precedence to each of the mobile stations using the common communication line, based on the number of base stations to which each of the mobile stations concurrently makes communication, and (c) abandons low-rate voice frames at a constant ratio among voice frames of a mobile station to which a low order of precedence is assigned.

Abstract: There is provided a device and method for transmitting packet data in a mobile communication system. A sub-code generator generates a plurality of sub-codes with the same or different code rates for the input of a PLP (Physical Layer Packet) information bit stream. A controller determines a minimum data rate by which the number of the modulation symbols of a sub-code generated by a predetermined modulation method is equal to or greater than the number of transmittable modulation symbols for each time period. A symbol pruner prunes part of the modulation symbols of the sub-code to make the number of the modulation symbols of the sub-code equal to the number of transmittable modulation symbols for the time period, if the number of the modulation symbols of the sub-code is greater than the number of transmittable modulation symbols for the time period.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.

Abstract: A method and apparatus for achieving the fastest possible data transmission rate, symmetric, near symmetric, or a specific data transmission rate between multiple analog modems. The invention comprises a multimedia unit comprising of two (or more) digital modems and a controller section. The controller provides the interface between the two (or more) digital modems. When a user attempts to send data from a first analog modem to a second analog modem, the user calls the first digital modem in the network. Next, the first digital modem establishes a connection with the second digital modem through the controller section which is partitioned in two segments. Controller segments may be co-located or located in different locations and connected through either Internet or PSTN. Then, the second digital modem dials up the second analog modem under direction of the controller.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: A system and method for providing a configurable signal processing circuit for a field configurable radio frequency communication system that is adaptable to be configured to function with a variety of signaling schemes or waveforms, and including an intermediate frequency (IF) digital signal processing circuit. A “tool box” of configurable signal processing circuits is available for processing multi-bit digital signals into and out of the IF circuit. Control registers receive digital instructions to select, interconnect and configure various circuits from the tool box to provide added signal processing for the selected the transmitter or receiver mode of operation as a function of the selected signaling scheme.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

Abstract: A modem and method for adjusting data transmission speed of the modem is provided. The modem, installed between a subscriber's terminal and an external modem for relaying communication, includes a timer for determining data transmission speed from the external modem, and a timer controller for performing a training process for determining data transmission speed of a line connecting the modem and the external modem. The timer controller determining a clock value of the timer based on the data transmission speed of the line determined by the training process. Accordingly, the data transmission speed of the model can be adjusted according to the data transmission speed of the line.

Abstract: A method and an apparatus for the transformation of a signal on a four-wire line are proposed where the signal comprises of discrete amplitude height levels that are intended for a conversion into a corresponding analog signal with amplitude height levels suitable for a two-wire line and the analog signal is intended for a data communication unit that connects to the two-wire line and which has a predefined amplitude resolution for the analog signal. The amplitude height levels of the signal on the four-wire line are transformed in such a way in the domain of the four-wire line that the number of amplitude height levels which the communication unit can discern in the analog signal match a presetable criterion.

Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: A network of localizers determines relative locations in three-dimensional space to within 1 cm by cooperatively measuring propagation times of pseudorandom sequences of electromagnetic impulses. Ranging transmissions may include encoded digital information to increase accuracy. The propagation time is determined from a correlator circuit which provides an analog pseudo-autocorrelation function sampled at discrete time bins. The correlator has a number of integrators, each integrator providing a signal proportional to the time integral of the product of the expected pulse sequence delayed by one of the discrete time bins, and the non-delayed received antenna signal. With the impulses organized as doublets the sampled correlator output can vary considerably in shape depending on where the autocorrelation function peak falls in relation to the nearest bin. Using pattern recognition the time of arrival of the received signal can be determined to within a time much smaller than the separation between bins.

Abstract: A GPS receiver has a plurality of data demodulator circuits assigned to a plurality of GPS satellites, respectively, and a data memory which stores detailed orbit information of the GPS satellites. The GPS receiver searches for satellites the detailed orbit information of which was stored in the memory previously. When these searched GPS satellites are acquired, the GPS receiver executes satellite frame synchronization determination processing to check for an agreement among predetermined data included in satellite data transmitted from the acquired GPS satellites. When the searched GPS satellites cannot be acquired or the predetermined data do not agree, the GPS receiver executes a single-satellite frame synchronization determination processing to check for an agreement of predetermined data included in a plurality of frames of the satellite data. The GPS receiver starts positioning processing in response to an establishment of agreement to calculate its position.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion. with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The spectral allocation can be varied by varying a stop frequency thereof, while maintaining a substantially constant start frequency, so as to mitigate undesirable high frequency content of the bandwidth. Alternatively, both start and stop frequencies may be varied.

Abstract: An apparatus and method for dynamic bit allocation for line-connected multicarrier systems, which allows high-quality data transmission, even when the interference signals are varying with time, in a simple and cost-effective manner.

Abstract: A system and method for accounting for clock slew during autobauding. Upon identifying an AT command and the baud rate of the incoming data stream, the present invention accounts for clock slew in one of two ways, depending upon the baud rate of the incoming data stream. If the baud rate of the incoming data stream is 9600 or greater, the present invention accounts for slew by utilizing a feature associated with ASCII characters and RS-232 protocol, that is the stop bit being nicely framed on both sides by spaces. This feature is used to determine whether negative or positive clock slew exists. If negative clock slew exists and it is determined that negative clock slew falls within a certain threshold, a sample is skipped. If positive clock slew exists and falls within a certain threshold, positive clock slew is converted to negative clock slew by taking an extra sample.

Abstract: In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

Abstract: A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

Abstract: A system and method is presented for reducing the power consumed by a line driver driving a signal to be transmitted through a communications media. The preferred method includes the steps of: (1) delaying the signal; (2) determining whether the signal has reached a predetermined threshold value; (3) increasing power supplied to the line driver in response to an indication from the determining step that the threshold has been reached; and (4) delivering the delayed signal to the line driver. The preferred system includes: (1) a digital signal processor; (2) a line driver; (3) a digital delay line disposed between the digital signal processor and the line driver; and (4) a power regulator disposed between the threshold detector and the line driver. The system and method, while applicable to many communications formats, is particularly applicable to communications methods transmitting signals having a relatively large dynamic range, such as xDSL communications techniques.

Abstract: The invention relates to an interface with parallel transfer channels for transmission of a number of parallel data signals and, possibly, command signals between associated outer connections and associated circuit points in an electronic assembly. A synchronization signal connection carries a synchronization signal indicating the time base for the parallel-transmitted signals. Selected examples of the transfer channels each contain an individually controllable delay device for setting a time delay for a signal transmission in the relevant transfer channel. Furthermore, a control device is provided in order to sense, in each selected transfer channel, the actual value of the relative phase of the data signal with respect to the associated, accompanying synchronization signal, and to control each of the delay devices as a function of the respectively sensed actual value, in the sense of matching the actual value to a predetermined, common nominal value.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: By providing an index that stores information about how to access each grouping of elements in an interleaved data stream and each element within each grouping, random access to each element in the interleaved data stream can be achieved. The index may store a temporal offset for each grouping for interleaved data streams in which the order of data samples in the interleaved data stream is different from the order in which those data samples are used to present the data stream. The information that allows each element in a grouping to be accessed may include information defining the length of each element, or information describing the relative position of each element in a grouping, such as a map table. Such a map table may have an entry for each data type, wherein each entry includes an indication of information used to access a sample of the data type.

Abstract: A multi-carrier communication system such as an OFDM or DMT system has nodes which are allowed to dynamically change their receive and transmit symbol rates, and the number of carriers within their signals. Changing of the symbol rate is done by changing the clocking frequency of the nodes' iFFT and FFT processors, as well as their serializers and deserializers. The nodes have several ways of dynamically changing the number of carriers used. The selection of symbol rate and number of carriers can be optimized for a given channel based on explicit channel measurements, a priori knowledge of the channel, or past experience. Provision is made for accommodating legacy nodes that may have constraints in symbol rate or the number of carriers they can support.

Abstract: A transmitter comprises a demodulation means for demodulating inputted stream data to digital data, and outputting the digital data to a digital interface; a decoding means for decoding the digital data to obtain an analog signal; and a format conversion means 125 for converting the format of the analog signal, and outputting the analog signal to an analog interface. A recorder comprises a judgement means for judging whether the inputted digital data is recordable by the recorder or reproducible after recording; a data recording means for recording the digital data on a recording medium when the judgement means judges that the digital data is recordable; and a coding means for coding the analog signal when the judgement means judges that the digital data is unrecordable. Therefore, the data outputted from the transmitter such as a set-top box can be reliably recorded by the recorder.