Abstract: An integrated circuit is provided for reducing scale of flip-flops which can be connected in the form of a shift register by the switching operation, in order to facilitate the test during the manufacture of an integrated circuit (gate array). One selector for switching a clock signal for the flip-flops to either of a system clock signal and a scan clock signal is provided not for each of the sequential circuits, but for each of the clock systems for these sequential circuits. In a case of a gate array, for example, this allows a reduction of three gates for each flip-flop to be realized.

Abstract: A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the different potential levels from the driving terminals in response to the data signals. The shift register includes an input terminal, an output terminal, a control terminal, a control circuit, a first shift circuit, and a second shift circuit. The first shift circuit has an input coupled to the input terminal of the shift register and the control circuit, and an output coupled to the control circuit. The second shift circuit has an input coupled to the control circuit and an output coupled to the output terminal of the shift register.

Abstract: A shift register includes a plurality of alternating shifting and latching sections connected in cascade. The phases of clocks (CLK, CLKB) for driving transmission gates (10, 14) of the shifting sections advance in phase relative to the phases of clocks (CLK, CLKB1) for driving transmission gates (12, 16) of the latching sections. The ON-resistance of the transmission gates (10, 14) of the shifting sections is sufficiently larger than that of the transmission gates (12, 16) of the latching sections, so that even when both of the clocks CLK and CLKB are at H or L levels due to delay imparted by inverters included in a clock generator, data to be latched is always given priority over data to be shifted. Thus, the shift register is free of a race condition which otherwise would be caused by a phase difference between the driving clocks.

Abstract: An improved shift register assembly having an integrated multi-phased dynamic shift register with a corresponding multi-phased driving buffer for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line thus reducing the number of input lines needed to address such an array. Furthermore, the multi-phased operation of the shift register allows for faster operation than tyhat of a traditional shift register setup.

Abstract: The synthesizer of the present invention is a multiple clock synthesizer for generating multiple clock signals with improved clock width and position accuracy. Within the synthesizer an oscillator provides a train of pulses corresponding to a base signal. A plurality of delay devices, formed of differing lengths of cables, are coupled to the oscillator with each cable providing a different delay to the train of pulses to in turn provide a plurality of delayed clocking signals. A plurality of registers, each having, a clocking input, a plurality of output taps, and load inputs and corresponding in number to the plurality of delay devices receive on their clocking inputs a delayed clocking signal from an associated one of the plurality of delay devices.

Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.

Abstract: An input/output circuit wherein a plurality of data lines are provided with a serial/parallel conversion means common to all, so that the circuit is enabled to consume less power and draw a reduced instantaneous current in its operation and be fabricated in an integrated circuit form.

Abstract: A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of the sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity.

Abstract: An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween.

Abstract: A logic integrated circuit of the scan path system comprises a combination circuit and a shift register associated to the combination circuit and including a plurality of cascaded flipflops. The shift register has a scan input, a clock input, a scan control input, and a scan output. A scan input terminal is connected to the scan input of the shift register, and a clock terminal is connected to the clock input of the shift register. A scan output terminal is connected to the scan output of the shift register. Further, there is provided a counter having an input connected to the clock terminal and an output connected to the scan control input of the shift register. This counter has a frequency division ratio equivalent to the stage number of the flipflops in the shift register, so that the shift register is switched between a shift register mode and a normal mode by the frequency division signal from the counter.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: For a plurality of logic units which are organized into scan-path groups, a scan-path self-testing circuit is provided which comprises a clock source and a plurality of gates for supplying the clock pulse to the logic units when selectively enabled. To give flexibility to group organization of the logic units, the gates are provided in a one-to-one relationship with the logic units. Bit positions of a register are associated respectively with the gates. A scan path controller selects one of the scan-path groups and writes a logic 1 into the register bit positions which are associated with the logic units of the selected scan-path group.

Abstract: A gated shift register includes a first set of 16 storage devices and a second set of 16 storage devices with interconnection circuitry for configuring the first set of 16 storage devices as a 16 bit shift register. The second set of storage devices is coupled between the outputs of the first set of storage devices and 16 output terminals of the gated shift register and transfers the outputs from the first storage devices to the output terminals when a transfer input terminal is at a first logic state, and isolates the first storage devices from the output terminals and retains the data at the output terminals when the transfer input signal switches to a second logic state. The gated shift register also includes power monitor and control circuitry for supplying standby battery voltage to the circuit when the primary power source becomes unavailable.

Abstract: In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

Abstract: A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.

Abstract: A serial-to-parallel converter has a number of memory cells connected in series for successively shifting input data in synchronism with a shift clock. The content of each memory cell is transferred by a latch circuit. The memory cells are provided with input terminals so that they can be set to "1" or "0" simultaneously before the entry of input data. This resetting, or presetting, reduces the number of reversals of the output polarity of the memory cells and hence the power consumed by the circuit can be diminished.

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation.

Abstract: A shift register stage (20) for LSI and VLSI circuits is disclosed and includes a first latching circuit (21) responsive to a data input and for providing a first data output; control circuitry (23) responsive to the first data output and to a parallel data input for providing as a controlled data output a replica of the first data output or a replica of the parallel data input as a function of a control signal; a second latching circuit (25) responsive to the controlled data output and for providing a second data output; and a third latching circuit (27) responsive to the second data output and for providing a third data output. Also disclosed is a shift register (30) for LSI and VLSI circuits which advantageously utilizes the foregoing shift register stage of the invention and which provides for AC or delay testing of an integrated circuit which includes two of such shift registers (30, 60) and a logic network (50) interposed therebetween.

Abstract: A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.

Abstract: A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.

Abstract: A power-saving serial data transfer circuit for outputting an inputted digital data signal through a plurality of serially connected shift register cells comprises n (=m.times.k) cells in k groups each containing m serially connected cells. A digital data signal is applied commonly to the first-stage cells of the groups and inputted in a time-wise segmented sequence to the cells by shift pulses with different phases. The inputted data signal is shifted through the cells within the same groups and is inputted to the last-stage cells of the groups. The inputted data signal is also outputted through a multiplexer connected to the last stage cells.

Abstract: A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the input logic signal. A first storage section is included for either enabling storage in the first storage section of an electric charge corresponding to the voltage level of the amplified and inverted input logic signal, or disabling storage in the first storage section of the electric charge, selectively in response to a first control signal. The stored electric charge is converted to an intermediate logic signal having a predetermined voltage level. Each memory cell additionally includes a second amplifier, fed by the intermediate logic signal, for amplifying and inverting the logic state of the intermediate logic signal.

Abstract: A wafer-scale integrated circuit wherein a plurality of memory cells on a wafer are connectable from a port to form a chain memory looping away from and back to the port by means of a serial connection of forward moving data registers and a serial connection of backward moving data registers between cells, has a reduced risk of any individual, otherwise functional cell being non-functional as a result of a failure elsewhere on the wafer of an associated global signal line by achieving a reduction in the numbers of global lines by providing the clock signal for controlling the shifting of data in the registers between the cells in parallel with the data, the inter-cell clock operating a multiple clock pulse generator in each cell.

Abstract: A register circuit which is used to asynchronously monitor any data or logical function (or functions) and be able to retain the status of the monitoring until the register is interrogated whereupon the register is automatically reset and able to receive or monitor another status signal.

Abstract: A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).