Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Abstract: A shift register capable of reducing power consumption is provided. The shift register includes: a clock signal supply line for supplying a clock signal; a plurality of selectors coupled to the clock signal supply line to generate driving signals in response to sampling signals; and a plurality of stages respectively coupled to the selectors to generate the sampling signals in response to the driving signals, wherein at least one of the selectors is adapted to generate at least one of the driving signals in response to a previous one of the sampling signals supplied from a previous one of the stages and a next one of the sampling signals supplied from a next one of the stages.

Abstract: The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n?2) pieces of basic circuits which are connected vertically in multiple stages.

Abstract: A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on.

Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.

Abstract: Each stage of a shift register circuit has an input section (60) and an output section (62). The input section of each stage comprises an input section drive transistor (Tdrive) for coupling a first clocked power line voltage (Pn) to the output of the input section (60), an input section compensation capacitor (Ci) for compensating for the effects of a parasitic capacitance of the input section drive transistor (Tdrive) and a first input section bootstrap capacitor (C2) connected between the gate of the drive transistor and the output of the input section. The input section (60) of each stage uses the output (Rn-i) of the input section (60) of at least one preceding stage as a timing control input for controlling a bootstrap function, and the output section (62) of each stage comprises a circuit which receives the outputs of multiple input sections (60) as timing signals for generating output signals for the output loads (64).

Abstract: A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The reset module is electrically coupled between the receiving module and the enabling module for receiving a reset signal to reset the pre-charge signal.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N?1)th shift register and an output of a (N?A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.

Abstract: A shift register and a shift register apparatus are provided. The shift register includes a plurality of shift register apparatus, and each shift register apparatus comprises a pre-charge circuit, a pull-up circuit and a pull-down circuit. The pre-charge circuit is used for sampling an input signal according to a first clock signal and a second clock signal respectively and generate a first charging signal and a second charging signal respectively. The pull-up circuit is coupled to the pre-charge circuit. The pull-up circuit receives the third clock signal and the first charging signal to output an output signal accordingly. The pull-down circuit is coupled to the pre-charge circuit and the pull-up circuit. The pull-down circuit receives the fourth clock signal and the second charging signal to decide whether to couple the output signal to a common potential.

Abstract: A method forms a feature pattern on a substrate by exposing the substrate, using a mask having a pattern of features thereon, with illumination having a first set of settings. The substrate is exposed a second time, using the same mask having the pattern of features thereon, with illumination having a second set of settings. The mask having the pattern of features thereon remains stationary between the two illumination exposures of the substrate.

Abstract: Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: A shift register includes M (M is an integer larger than two) stages of transfer elements and a control circuit. The M stages of the transfer elements transfer N (M>N, N is an integer larger than one) data signals sequentially input within one cycle. To the control circuit, N clock signals and a control signal are input within the one cycle and the control circuit supplies a shift clock signal to N stages of the transfer elements among the M stages of the transfer elements and supplies a skip fixed logic signal to (M?N) stages of the transfer elements among the M stages of the transfer elements based on the control signal.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: An exemplary shift register includes plural shift register units (S1˜Sn). All the shift register units receive either a first clock signal or a second clock signal, and the shift register units output a plurality of shift register signals in sequence. An output of a previous shift register unit is an input of the next adjacent shift register unit.

Abstract: A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words.

Abstract: A processing element includes a shift register including n stages of registers mutually connected in series. Data held among the n stages of registers is rotated in synchronization with a clock signal. A number-of-stages determining circuit determines the number of stages to be used among the n stages of registers. An output terminal of the register in the last stage connects to an input terminal of the register in the first stage.

Abstract: An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.

Abstract: A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

Abstract: A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

Abstract: A signal-driving system for constructing gate signals of liquid crystal display (LCD), includes a plural stage of cascaded shift register units. Each stage of shift register unit includes a first pull-up switch unit, which is turned on for outputting a gate pulse on an output of this stage, based on either the first clock signal or the second clock signal; a pull-up driving unit, which is used for providing a driving pulse via a node for driving the first pull-up switch unit; a first pull-down switch unit, which is turned on to connect the output to a low-level voltage source; a second pull-down switch unit, which is turned on to connect said node to the low-level voltage source; a carry buffer unit, which is used for providing a control pulse on the second pull-down switch unit of previous stage, based on either the first clock signal or the second clock signal, and thereby ensuring operation of each stage independent of gate pulse signals outputted from the other stages.

Abstract: The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n?1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n?1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

Abstract: The invention provides a shift register which can function normally even with an abnormal register or a broken register while suppressing the manufacturing cost as little as possible. The shift register of the invention includes n regular registers (SR(1) to SR(n)) connected in series and n output lines (L1 to Ln) corresponding to the n regular registers, r (r?n) redundant registers (SR(n+1) to SR(n+r)) connected in series to the n regular registers, and a switch circuit for selectively connecting the regular and redundant resistors to output lines. The switch circuit connects the n regular registers to the corresponding output lines in a normal state, connects normal registers of upper and lower stages of the broken register by skipping and disabling the broken register if any, and connects normal regular registers and the same number of redundant registers as the broken registers to the n output lines.

Abstract: A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32?) of its successor (30?) share a common capacitive node (33).

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

Abstract: An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.

Abstract: An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM), the fuses are electrically connected to respective cells of the shift register, and the output of the shift register is electrically isolated from an output buffer. When the chip is put into test mode, the electrical connections between the fuses and the shift register bits are broken, leaving the fuse information isolated in the shift register. The test mode also connects the output of the shift register to the output buffer and the output of the first shift register bit is seen on the output pin. The rest of the shift register information bits are serially shifted out of the shift register by toggling the CEB pin.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift register and right shift and left shift control signals. Dependent on the input signals, the input circuit portion drives an input node coupled to the latching circuit portion with a data value to be shifted which corresponds to data from one of the previous and next single-latch circuits.

Abstract: A space-efficient, multi-cycle barrel shifter circuit for shifting data inputted into the circuit by a shift value over multiple clock cycles which circuit includes: (a) a load module adapted to receive a load signal and the data, the load module coupled to the shift module and configured to load the data into the shift module upon receipt of a load signal; (b) a register module coupled to the shift module and to the load module, where the register module is a register adapted to receive a clock signal and configured to pass the data through the shift module with each clock cycle; (c) a constant shift module coupled to the register module and the shift module and configured to shift the data by a constant amount with each clock cycle; and (d) a control module coupled to the shift module and the load module, the control module capable of generating a command signal for each elementary shifter in the shift module for each clock cycle based upon the shift value, the command signal determining the amount of shift

Abstract: A clock signal generator comprises a clock input CK and N stages where N is greater than three. Each of the stages comprises a transmission gate M3, M4 which passes clock pulses from the clock Input CK in response to a control signal a from the preceding stage. A control signal generating circuit M5, M6, D7, M8 supplies a control signal e to the succeeding stage when the control signal a from the preceding stage and the clock pulse from the transmission gate M3, M4 have ended. The control signal generating circuit M5, M6, D7, M8 ends the control signal e when the succeeding stage produces its control signal F.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: The present invention provides a power consumption reduced register circuit which performs data processing in low power consuming and no wasteful manner. Reduction in power consumption of a synchronous circuit for accepting and outputting of data in synchronization with clock signals is achieved. An input to and output from a register are monitored and compared for outputting a determination result signal. A logical sum of an input determination control signal and the determination result signal is obtained in an OR gate, the output of which is latched to a D type flip-flop in synchronization with an invented signal of a clock signal input to the register. A logical product of the output of the flip-flop and the clock signal is obtained by an AND gate, the output signal from which is applied to the register as a clock signal.

Abstract: A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number is thereafter simultaneously shifted right or shifted left a given shift amount to effect a dual right or dual left shift function.

Abstract: A thermostat includes a case, including an exterior, that is made of conductive material. A cover plate is made of a conductive material. The cover plate is connected to the case to define a sealed interior. The cover plate has a contact projecting into the sealed interior. The contact is fixed with respect to the case and has an interior contact position. An insulator sheet is disposed between the case and the cover plate. A blade is disposed in the sealed interior. A second end of the blade moves between a first position where it abuts the contact position of the contact and a second position where it is spaced from the interior contact position of the contact. A resistor is mounted on a first end of the blade. The resistor is disposed between the cover plate and the blade in the sealed interior of the case. The resistor has a first side facing and abutting the cover plate, and a second side facing and abutting the blade so that the resistor is electrically connected between the cover plate and the blade.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Abstract: A new class of shift registers that shift the contents of a 2.sup.n bit length register up to 2.sup.n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift either left or right. A general implementation of this class of shift registers comprises the following hardware: 2.sup.n D flip-flops or D latches for the data register positions of the shift register; logic for each of the 2.sup.

Abstract: An imaging device for generating an image signal includes an image sensing device for producing an image signal subject to one or more clock signals and a circuit for generating one or more of the clock signals, wherein the clock signal generating circuit is responsive to a programmable input signal for adjusting a duty cycle of at least one of the clock signals. In particular, by clocking two recirculating shift registers out of phase and parallel loading them with a programmable bit pattern to produce the output clock signals, the frequency of an input clock that is required to produce the output clock signals can be reduced by half.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: This invention relates to the structure of multiple registers used in image signal processing, and aims to simplify the register structure and to reduce the power consumption of the registers and the time required for testing an image signal processing LSI with the registers. A semiconductor integrated circuit according to the invention has a clock generation circuit and a clock buffer circuit for generating a plurality of clock signals, a register group including a plurality of registers connected in series and operable in synchronism with the clock signals, at least one combinational circuit connected to the register group, and means for selecting one of a normal operation mode and a scan test mode for the register group. The clock generation circuit receives a system clock CP.sub.IN, a scan test mode selection signal S.sub.MODEN, and clock CPS.sub.IN, and outputs a clock .phi. and a clock (.phi..sub.1 bar) controlled by the signal S.sub.

Abstract: An XY-address solid-state image pickup apparatus comprises a pixel array made up a plurality of pixels two-dimensionally arranged and horizontal and vertical scanning circuits for reading the signal from the pixel array. Each scanning circuit comprises a plurality of unit stages cascaded, each unit stage comprising a plurality of first shift register units cascaded and a single second shift register unit which is associated with the plurality of first shift register units and which is driven by a clock different from the clock that drives the plurality of first shift register units. Each unit stage further comprises a first switch and a second switch. The input to the first unit of the first shift register units is also fed to the second shift register unit via the first switch. The output of the second shift register unit is fed to each of the plurality of first register units within the unit stage via the second switch.

Abstract: The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said integer, and a plurality of second shift registers corresponding in number to the integer and each having a clocking input coupled to a respective one of the first phase shifted signals. The second registers produce a plurality of second phase shifted signals having leading edge transitions separated from each other by displacements corresponding to the transitions of the master clock signal. The second phase shifted signals are then combined to generate the lower frequency clock pulses, which may be used, e.g., in the clocking of a charge coupled device image sensor.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.

Abstract: A serial data receiving device comprises a first memory means for storing serial data while shifting the data bit by bit whenever receiving each one bit of the data and converting the serial data into parallel data when all the bits constituting the serial data are stored; a first detecting means for detecting the storage of all the bits constituting the serial data in the first memory means, a second memory means for storing a signal allowing the serial data to be received in accordance with the detection result by the first detecting means, and a first control means for controlling the reception of the serial data (outputting a hand-shake signal or transfer clock, for example) in accordance with the stored contents in the second memory means. A serial data transfer apparatus is equipped with the serial data receiving device, wherein the receiving device controls the transfer of the serial data.

Abstract: An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.

Abstract: The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.

Abstract: A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduces software overhead significantly when multiple registers must be modified.