Inspecting Printed Circuit Boards Patents (Class 382/147)
  • Patent number: 8406503
    Abstract: A mounted component inspection apparatus according to the present invention includes: a component library holding inspection information; an inspection processing unit for inspecting a component under inspection using the component library; a match rate acquisition unit for acquiring a match rate indicating the degree to which the inspection information is suitable for the inspection by the inspection processing unit, on the basis of the result of the inspection by the inspection processing unit; and a judgment unit for selecting the inspection information having a higher match rate, of the inspection information before updating and the inspection information after updating. The component library can hold the inspection information before and after updating, and the inspection processing unit carries out the inspection using the inspection information before and after updating held in the component library.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventor: Yoichiro Ueda
  • Patent number: 8401274
    Abstract: A computer displays an image of an object which has been created by photographing by a photographing portion in a setting mode. Further, height threshold-value data is received according to an input from outside through a key board. Based on height information detected from the image created by photographing and based on the received threshold-value data, a partial image having height information specified by the threshold-value data is extracted from the image created by photographing and then is displayed. In a driving mode, the computer displays an image acquired by photographing the object, and extracts a partial image having height information specified by the threshold-value data, based on the height information detected from the image created by photographing and the threshold-value data preliminarily-received in the setting mode. The image data extracted in the driving mode is utilized for inspections of defects in the object.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: March 19, 2013
    Assignee: Omron Corporation
    Inventors: Hiroyuki Hazeyama, Yuki Taniyasu, Shiro Fujieda
  • Patent number: 8401273
    Abstract: A measurement tool apparatus for evaluating degradation of pattern features in a semiconductor device manufacturing process. The measurement tool apparatus detects variations in the patterns from SEM images thereof and extracts pattern edge points along the circumference of each pattern. The measurement tool apparatus compares the pattern edge points to corresponding edge points of an ideal shape so as to determine deviation of the patterns. Metrics are derived from analysis of the deviations. The measurement tool apparatus uses the metrics in calculating an index representative of the geometry of edge spokes of the pattern, an indicator of the orientation of the edge spokes, and/or anticipated effects of the edge spokes on device performance.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: March 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Momonoi, Atsuko Yamaguchi, Taro Osabe
  • Patent number: 8379963
    Abstract: This solution relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a cell computing system. The invention provides a high performance machine vision system over the prior art and provides a method for executing image processing applications on a Cell and BPE3 image processing system. Moreover, implementations of the invention provide a machine vision system and method for distributing and managing the execution of image processing applications at a fine-grained level via a PCIe connected system. The hybrid system is replaced with the BPE3 and the switch is also eliminated from the prior in order to meet over 1 GB processing requirement.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Moon J. Kim, Yumi Mori, Hiroki Nakano, Masakuni Okada
  • Patent number: 8379229
    Abstract: Embodiments of the present invention enable generation of a simulated reference bitmap image that corresponds to a dot-pattern image. Certain applications of the present invention are its use in various embodiments of a system for inspection of a printed circuit board (“PCB”) substrate. In embodiments, a dot-pattern image and user-input configuration parameters are used to create an initialized simulated reference bitmap, and the dot pattern is mapped onto the reference bitmap using a scaling factor. In embodiments, reference bitmaps of individual sections of a dot-pattern image may be generated separately.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: February 19, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Ali Zandifar
  • Patent number: 8369603
    Abstract: An inspection method for inspecting a device mounted on a substrate, includes generating a shape template of the device, acquiring height information of each pixel by projecting grating pattern light onto the substrate through a projecting section, generating a contrast map corresponding to the height information of each pixel, and comparing the contrast map with the shape template. Thus, a measurement object may be exactly extracted.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: February 5, 2013
    Assignee: Koh Young Technology Inc.
    Inventors: Joong-Ki Jeong, Yu-Jin Lee, Seung-Jun Lee
  • Patent number: 8363922
    Abstract: A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maria Gabrani, Paul Hurley
  • Patent number: 8358832
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. This invention demonstrates a method where high accuracy navigation to the site of interest within a relatively large local area (e.g. an area 200 ?m×200 ?m) is possible even where the stage/navigation system is not normally capable of such high accuracy navigation. The combination of large area, high-resolution scanning, digital zoom and registration of the image to an idealized coordinate system enables navigation around a local area without relying on stage movements. Once the image is acquired any sample or beam drift will not affect the alignment. Preferred embodiments thus allow accurate navigation to a site on a sample with sub-100 nm accuracy, even without a high-accuracy stage/navigation system.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: January 22, 2013
    Assignee: FEI Company
    Inventors: Richard J. Young, Chad Rue, Peter D Carleson
  • Patent number: 8355562
    Abstract: A pattern shape evaluation method and semiconductor inspection system having a unit for extracting contour data of a pattern from an image obtained by photographing a semiconductor pattern, a unit for generating pattern direction data from design data of the semiconductor pattern, and a unit for detecting a defect of a pattern, through comparison between pattern direction data obtained from the contour data and pattern direction data generated from the design data corresponding to a pattern position of the contour data.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: January 15, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Ryoichi Matsuoka, Akiyuki Sugiyama
  • Patent number: 8351657
    Abstract: The invention relates to a method, which comprises the capturing of image data representing a physical object using an electronic device. First visual objects are determined in the image data. Second objects are determined among the first visual objects. Position information is determined for the second visual objects within the physical object. Third visual object are obtained based on the position information from object data storage. The third visual objects are matched to the first visual objects and differences between third visual objects and the first visual object are indicated to a user.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: January 8, 2013
    Assignee: Nokia Corporation
    Inventors: Kaj Makela, Jukka Nurminen, Olli Immonen, Petteri Saarinen, Panu Vartiainen
  • Patent number: 8351682
    Abstract: This invention enables information on a connection wiring with a substrate of a mounted component to be accurately and easily inputted in an X-ray examination apparatus. In teaching of a substrate examination, when a user inputs a two-dimensional region of a component to be examined with respect to a visible light image of the substrate, three-dimensional data is generated for the relevant region, which data is then analyzed to acquire a center coordinate, the number, the number of rows, and the number of columns on a ball terminal connecting the component to the substrate. Results such as the center coordinate acquired in such a manner may be displayed. The visible light image for the substrate is displayed in a display field of a screen.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: January 8, 2013
    Assignee: Omron Corporation
    Inventors: Hideyuki Hayashi, Kunio Yoshida, Kiyoshi Murakami
  • Patent number: 8340393
    Abstract: A method for evaluating a feature. The method includes receiving an image of the feature and determining respective coordinates of a plurality of points on an edge of the feature in the image. A figure having a non-circular and non-linear shape is fitted to the plurality of points, and respective distances between the plurality of points and the figure are determined. A roughness parameter for the feature is computed using the respective distances. The method may be applied in the analysis of critical dimensions (CD) of integrated circuits and, particularly, in the measurement of the edge roughness of their features and components as imaged using electron scanning microscopy (SEM).
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: December 25, 2012
    Assignee: Applied Materials Israel Limited
    Inventors: Aviram Tam, Colin David Chase
  • Publication number: 20120301010
    Abstract: In a method for identifying components of a printed circuit board (PCB) using a computing device, the computing device connects to a digital scanner and a display device. The digital scanner scans a PCB to generate a PCB file. The method selects one or more location points from the PCB, locates a coordinate point for each location point according to the PCB file, and builds a coordinate relationship between each location point and the coordinate point. The method converts the PCB file into a PCB image using a visual graphic tool, searches a test point on the PCB image according to a name of a component of the PCB, identifies the component on the PCB according to the test point, and obtains a coordinate value of the component according to the coordinate relationship. The display device displays the name and the coordinate value of the component for users.
    Type: Application
    Filed: March 23, 2012
    Publication date: November 29, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHUAN-CHI LIU, HUI-CHI LO
  • Patent number: 8318391
    Abstract: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 27, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Moshe E. Preil, Xun Chen, Shauh-Teh Juang, James Wiley
  • Patent number: 8319962
    Abstract: The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chien-Chao Huang
  • Patent number: 8290239
    Abstract: An apparatus and method for automatically inspecting and repairing printed circuit boards includes an inspection functionality automatically inspecting printed circuit boards and providing a machine readable indication of regions thereon requiring repair. An automatic repair functionality employs the machine readable indication to repair the printed circuit boards at some of the regions thereon requiring repair. An automatic repair reformulation functionality automatically reinspects the printed circuit boards following an initial automatic repair operation, and provides to the automatic repair functionality a reformulated machine readable indication of regions thereon requiring repair.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: October 16, 2012
    Assignee: Orbotech Ltd.
    Inventors: Amir Noy, Gilad Davara
  • Patent number: 8285030
    Abstract: A technique for determining a set of calibration parameters for use in a model of a photo-lithographic process is described. In this calibration technique, images of a test pattern that was produced using the photo-lithographic process are used to determine corresponding sets of calibration parameters. These images are associated with at least three different focal planes in an optical system, such as a photo-lithographic system that implements the photo-lithographic process. Moreover, an interpolation function is determined using the sets of calibration parameters. This interpolation function can be used to determine calibration parameters at an arbitrary focal plane in the photo-lithographic system for use in simulations of the photo-lithographic process, where the set of calibration parameters are used in a set of transmission cross coefficients in the model of the photo-lithographic process.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: October 9, 2012
    Assignee: Synopsys, Inc.
    Inventors: Xin Zhou, Yaogang Lian, Robert E. Gleason
  • Patent number: 8275188
    Abstract: A system for inspecting chips in a tray comprises a three-dimensional sensor, a focus computing unit, an image sensor and a focusing device. The three-dimensional sensor is used to obtain the height signals of surfaces of the chips. The focus computing unit calculates the focusing positions of chips. The surface inspection sensor is used to inspect the surfaces of the chips. The focusing device is used to bring the images of the surfaces of the chips into the focus of the image sensor.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: September 25, 2012
    Assignee: Cheng Mei Instrument Technology Co., Ltd.
    Inventor: Cheng Tao Tsai
  • Patent number: 8264535
    Abstract: The invention relates to a method for analyzing a group of at least two masks for photolithography, wherein each of the masks comprises a substructure of a total structure, which is to be introduced in a layer of the wafer in the lithographic process, and the total structure is introduced in the layer of the wafer by introducing the substructures in sequence. In this method, a first aerial image of a first one of the at least two masks is recorded, digitized and stored in a data structure. Then, a second aerial image of a second one of the at least two masks is recorded, digitized and stored in a data structure. A combination image is generated from the data of the first and second aerial images, which combination image is represented and/or evaluated.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: September 11, 2012
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Oliver Kienzle, Rigo Richter, Norbert Rosenkranz, Yuji Kobiyama, Thomas Scheruebl
  • Patent number: 8264534
    Abstract: A method for processing the image data of the surface of a wafer (2) recorded by at least one camera (5) is disclosed, wherein an image field (15) is defined for each camera (5) in such a way that the recorded image content is repeated after N recorded images. In an evaluation electronics (18) M utility programs (19) are determined, wherein M is equal to the number of recorded images after which the image content is repeated. The number M of utility programs (19) is adapted to the number N of images. Each of the M utility programs (19) of the plurality of recorded images is only fed with images having the same image contents in order to detect defects on the basis of the image contents of the images of the surface of the wafer. The results of the M utility programs (19) are respectively forwarded to a central program (20) in a sequential manner, which compiles a distribution of the defects present on the surface of the wafer (2) from the individual results of the M utility programs (19).
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: September 11, 2012
    Assignee: Vistec Semiconductor Systems GmbH
    Inventor: Detlef Michelsson
  • Patent number: 8260034
    Abstract: A technique for identifying a defect in an object produced by a controllable process. A first type of data generated as a result of production of the object by the controllable process is obtained. A second type of data generated as a result of production of the object by the controllable process is obtained. The first type of data and the second type of data are jointly analyzed. A defect is identified in the object based on the joint analysis of the first type of data and the second type of data. By way of example, the controllable process comprises a semiconductor manufacturing process such as a silicon wafer manufacturing process and the object produced by the semiconductor manufacturing process comprises a processed wafer. The first type of data comprises tool trace data and the second type of data comprises wafer image data. The tool trace data is generated by a photolithographic tool.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: September 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lisa Amini, Brian Christopher Barker, Perry G. Hartswick, Deepak S. Turaga, Olivier Verscheure, Justin Wai-chow Wong
  • Patent number: 8243134
    Abstract: An optical reader includes an imaging device and an photographing optical system for reading images of an object such as a semiconductor wafer. An LED light source is provided as a dark field illumination light source for illuminating the object at an angle of illumination that deviates from the optical axis of the photographing optical system. The LED light source is supported by a swing-type support member having both ends secured to a housing of the optical reader using screws and nuts. This allows the angle and position of the dark field illumination light source to be adjusted so as to provide a first angle of illumination for illuminating the object directly with the illuminating light from the dark field illumination light source, or a second angle of illumination for illuminating the object by reflection from a half mirror that is disposed in an illumination optical system.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: August 14, 2012
    Assignee: Kowa Company Ltd.
    Inventors: Takahisa Mizuta, Hidetomo Sakiyama
  • Patent number: 8233697
    Abstract: A method and device generate digital still pictures of wafer-shaped elements, such as wafers or solar cells, which are transported in series on a conveyor belt during a production process. The device has a camera taking pictures of the wafer-shaped elements in sections step-by-step, in particular continuously taking digital pictures line-by-line (linear scanning) transverse to the transport direction, and then sampling the recorded image data. The device also includes a hardware-based image data processing unit, e.g. FPGA, for detecting edges of the wafer-shaped elements that indicate a beginning or an end of each of the wafer-shaped elements. The edge detection is for controlling the generation of the digital still pictures for visual inspection to find defective areas of the elements.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: July 31, 2012
    Assignee: Schott AG
    Inventor: Michael Stelzl
  • Patent number: 8229205
    Abstract: A pattern matching method for use in manufacturing a semiconductor memory device increases a pattern matching rate between a GDS image and an SEM image. The pattern matching method includes extracting a scanning electron microscope (SEM) image and a graphic data system (GDS) image to perform a pattern matching; performing a two-dimensional Fourier transform (FFT) for the extracted GDS image and analyzing a low spatial frequency; deciding whether or not a pattern is a repeated pattern or non-repeated pattern by using the analyzed low spatial frequency; and limiting an X/Y range for a pattern matching when the decision result is for the repeated pattern, and then performing the pattern matching between the SEM image and the GDS image.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Kyeong Hyon, Young-Seog Kang, Sang-Ho Lee, Hyun-Jong Lee
  • Patent number: 8194089
    Abstract: A measurement tool overlay program that after initial placement in or around the object field, automatically identifies (in ‘expand’ mode) any distance between objects by other programs that are displayed on the screen relative to a starting point between the objects. Measures is provided of the dimensions of any object, or group of objects by accessing the picture elements (pixels) in the memory associated with the display screen. Alternate embodiments according to the present invention operate in ‘contract’ mode. In ‘contract’ mode, the present invention also provides the measurements of an end user-placed rectangular boundary around any given object(s), or distance between outside edges of clusters of object(s) immediately. The box will contract to the size (edge) of the area as defined by pixels, which may be part of one or more objects within the area and provide the dimensions automatically.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: June 5, 2012
    Inventors: Wolfgang Ante, Craig Lemoine Hockenberry, Corey Bryant Marion, Travis James Zuker, Talos Shu-Ming Tsui, Anthony John Piraino, David Edward Lanham, Gedeon Paul Maheux, David Andrew Brasgalla, Mindy Karol Weaver
  • Patent number: 8194969
    Abstract: A visual inspection apparatus includes an image-data acquisition unit for acquiring plural pieces of image data A to C on an inspection target, image comparison units for comparing the image data A to C with each other thereby to create plural pieces of sign-affixed difference-image data D and E, the image data A to C being acquired by the image-data acquisition unit, difference-image comparison units for determining the difference between the sign-affixed difference-image data D and E created by the image comparison units, and a judgment unit for subjecting, to a threshold-value processing, difference data F between the difference-image data D and E, the difference data F being acquired by the difference-image comparison units, obtaining a detection sensitivity by enlarging the difference between an abnormal signal level of an image of an area where an abnormality exists from the visual inspection.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: June 5, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventor: Kei Shimura
  • Publication number: 20120128231
    Abstract: In order to inspect a board, firstly, a measurement area is set on a board, and reference data and measurement data of the measurement area are acquired. Then, a plurality of feature blocks is established by a block unit so as to include a predetermined shape in the measurement area, and a merged block is established by merging feature blocks overlapped in the feature blocks. Thereafter, a distortion degree is acquired by comparing reference data and measurement data corresponding to a feature block except for the merged block and/or the merged block, and the distortion degree is compensated for, to set an inspection area in the target measurement area. Thus, an inspection area, in which distortion is compensated for, may be correctly set.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 24, 2012
    Applicant: KOH YOUNG TECHNOLOGY INC.
    Inventor: Bong-Ha HWANG
  • Patent number: 8184897
    Abstract: One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's optical system under different focus conditions. Next, the system can determine a location in proximity to the iso-focal pattern where the aerial-image-intensity values are substantially insensitive to focus variations. The system can then use the location and the associated aerial-image-intensity values to determine an optical threshold and a resist bias. The optical threshold and the resist bias can then be used for modeling the photolithography process.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: May 22, 2012
    Assignee: Synopsys, Inc.
    Inventors: Jianliang Li, Lawrence S. Melvin, III, Qiliang Yan
  • Patent number: 8144973
    Abstract: A method for scanning a surface with a number of different illumination configurations, the method comprises capturing a plurality of images in a sequential manner during a single sweep, each image including one or more lines of pixels, sequentially altering an illumination configuration used to capture the plurality of images according to a predefined sequence of illumination configurations and shifts of the relative position of the imaging unit for capturing each of the plurality of images, and repeating the sequence of illumination configurations settings and associated image capture positions until a desired area of the surface is scanned, wherein said predefined shift is between 10 pixels and less then one pixel.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 27, 2012
    Assignee: Orbotech Ltd.
    Inventors: Tamir Margalit, Ram Oron, Amir Noy
  • Patent number: 8144972
    Abstract: The present invention relates to a method for manufacturing a printed circuit board and an apparatus for manufacturing the same; and, more particularly, to a method for manufacturing a printed circuit board and an apparatus for manufacturing the same capable of improving the degree of matching between contact holes and pads by correcting exposure position data of an exposing process for forming the pads according to positions of the contact holes.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chung Woo Cho, Seon Ha Kang, Young Hwan Shin, Jong Jin Lee
  • Patent number: 8139844
    Abstract: Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: March 20, 2012
    Assignee: KLA-Tencor Corp.
    Inventors: Chien-Huei (Adam) Chen, Yan Xiong, Jianxin Zhang, Ellis Chang, Tsung-Pao Fang
  • Patent number: 8131055
    Abstract: A method for assembly inspection is disclosed. The system may include obtaining a digital image of an assembled product, extracting images of one or more objects from the digital image of the assembled product, and recognizing each of the one or more objects as a component based on its extracted image and a library of standard components. The method may further include identifying one or more features of each recognized component, comparing each of the one or more identified features with a corresponding standard feature of the corresponding standard component, and determining an assembly fault if at least one of the one or more identified features does not match the corresponding standard feature.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: March 6, 2012
    Assignee: Caterpillar Inc.
    Inventors: Burton Roland Clarke, John Edward Norlin
  • Patent number: 8126258
    Abstract: In a method of detecting defects in patterns and an apparatus for performing the method, a first image of a detection region on a semiconductor substrate may be acquired. A second image may be acquired from the first image by performing a Fourier transform and performing a low pass filtering. The second image may be compared with a reference image so that the defects of the detection region are detected. Existence of the defect of the second image is determined using a relation value between a grey level of each of pixels of the second image and the reference image, respectively. When a defect exists, the horizontal and the vertical positions of the pixel where the relation value is minimum are combined to determine the position of the defect.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Sin Yang, Chung-Sam Jun, Jong-An Kim, Moon-Shik Kang, Ji-Hye Kim
  • Patent number: 8121391
    Abstract: An apparatus for measuring a thickness of a printed product conveyed in a conveying direction at a conveying speed. The apparatus includes a conveying device having a guide arrangement along which the printed product is conveyed at the conveying speed in the conveying direction, the guide arrangement including a measuring region that extends in the conveying direction of the guide arrangement. The apparatus further includes a measuring element operative to act on printed sheets of the printed product to measure the thickness of the printed product while the printed product is conveyed across the measuring region and through a measuring gap located between the measuring element and the guide arrangement. The measuring element is arranged to move toward the guide arrangement with a process timing and to move synchronously with the printed product at the conveying speed across the measuring region of the guide arrangement. The apparatus additionally includes an evaluation unit connected to the measuring element.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 21, 2012
    Assignee: Mueller Martini Holding AG
    Inventor: Hanspeter Duss
  • Patent number: 8121394
    Abstract: A method for manufacturing an electronic device is provided. The method includes: pressure-bonding a plurality of terminals of an electronic component to a plurality of electrodes formed on a surface of a transparent substrate, respectively, via an anisotropic conductive film to mount the electronic component on the transparent substrate; obtaining an image of the electrodes by imaging the transparent substrate with the electronic component mounted thereon from backside of the transparent substrate; measuring the number of indentations for each said electrode using the image of the electrode, the indentation being formed when the electrode is pressed by a conductive particle in the anisotropic conductive film; calculating an average and a standard deviation of the number of indentations per electrode throughout the transparent substrate; and calculating a probability that the number of indentations per electrode is less than a reference value on basis of the average and the standard deviation.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Miyauchi
  • Patent number: 8120767
    Abstract: The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: February 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chien-Chao Huang
  • Patent number: 8111901
    Abstract: A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns is disclosed. Simulation to obtain an image log-slope (ILS), normalized image log-slope (NILS), or any other characteristic of an image quality on edges of polygons in the circuit pattern obtained from circuit pattern data is performed. Properly printed edges and not-properly printed edges are identified according to a criterion of an ILS level. The original circuit pattern is separated into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: February 7, 2012
    Assignee: ASML Masktools B.V.
    Inventor: Peter Nikolsky
  • Patent number: 8111900
    Abstract: Various computer-implemented methods are provided. One method for sorting defects in a design pattern of a reticle includes searching for defects of interest in inspection data using priority information associated with individual defects in combination with one or more characteristics of a region proximate the individual defects. The priority information corresponds to modulation levels associated with the individual defects. The inspection data is generated by comparing images of the reticle generated for different values of a lithographic variable. The images include at least one reference image and at least one modulated image. A composite reference image can be generated from two or more reference images. The method also includes assigning one or more identifiers to the defects of interest. The identifier(s) may include, for example, a defect classification and/or an indicator identifying if the defects of interest are to be used for further processing.
    Type: Grant
    Filed: May 15, 2010
    Date of Patent: February 7, 2012
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: Kenong Wu, David Randall, Kourosh Nafisi, Ramon Ynzunza, Ingrid B. Peterson, Ariel Tribble, Michal Kowalski, Lisheng Gao, Ashok Kulkarni
  • Patent number: 8094920
    Abstract: A scanning electron microscope comprises an image processing system for carrying out a pattern matching between a first image and a second image. The image processing system comprises: a paint-divided image generator for generating a paint divided image based on the first image; a gravity point distribution image generator for carrying out a smoothing process of the paint divided image and generating a gravity point distribution image; an edge line segment group generation unit for generating a group of edge line segments based on the second image; a matching score calculation unit for calculating a matching score based on the gravity point distribution image and the group of edge line segments; and a maximum score position detection unit for detecting a position where the matching score becomes the maximum.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: January 10, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Akiyuki Sugiyama, Hiroyuki Shindo
  • Patent number: 8089622
    Abstract: A device for evaluating defects in the edge area of a wafer (6) is disclosed. The evaluation may also be performed automatically. In particular, the device includes three cameras (25, 26, 27), each provided with an objective (30), wherein a first camera (25) is arranged such that the first camera (25) is opposite to an edge area on the upper surface (6a) of the wafer (6), wherein a second camera (26) is arranged such that the second camera (26) is opposite to a front surface (6b) of the wafer (6), and wherein a third camera (27) is arranged such that the third camera (27) is opposite to an edge area on the lower surface (6c) of the wafer (6).
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 3, 2012
    Assignee: Vistec Semiconductor Systems GmbH
    Inventors: Andreas Birkner, Michael Hofmann, Wolfgang Vollrath
  • Patent number: 8082190
    Abstract: A method of assembling a utility meter having a plurality of components on a subassembly is disclosed herein. The method comprises associating an identification code, such as a barcode, with the subassembly and then entering the barcode associated with the subassembly into a first memory. Next, a lot identification code for each of a plurality of components of the subassembly is associated with the barcode of the subassembly in the first memory. The subassembly is then placed in the utility meter having an associated utility meter identification code. The utility meter identification code is then entered in a second memory and the utility meter identification code is associated with the barcode of the subassembly in the second memory. The first and second memory may be searched to determine lot identification codes for each of the plurality of components in the utility meter.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 20, 2011
    Assignee: Landis+Gyr, Inc.
    Inventors: Angela R. Cogar, John P. Junker
  • Patent number: 8073242
    Abstract: This invention relates to a SEM system constructed to create imaging recipes or/and measuring recipes automatically and at high speed, and improve inspection efficiency and an automation ratio, and to a method using the SEM system; a method for creation of imaging recipes and measuring recipes in the SEM system is adapted to include, in a recipe arithmetic unit, the steps of evaluating a tolerance for an imaging position error level at an evaluation point, evaluating a value predicted of the imaging position error level at the evaluation point when any region on circuit pattern design data is defined as an addressing point, and determining an imaging recipe and a measuring recipe on the basis of a relationship between the tolerance for the imaging position error level at the evaluation point and the predicted value of the imaging position error level at the evaluation point.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: December 6, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Miyamoto, Tomofumi Nishiura, Ryoichi Matsuoka, Hidetoshi Morokuma
  • Patent number: 8064068
    Abstract: A system for sensing a three-dimensional topology of a test surface is provided. A first illumination source generates first patterned illumination from a first point of view. A second illumination source generates second patterned illumination from a second point of view, the second point of view differing from the first point of view. An area array image detector simultaneously acquires at least first and second fringe images relative to the first and second patterned illuminations. A controller is coupled to the first and second sources and to the detector. The controller generates a height topology of the test surface based on images acquired while the first and second patterned illuminators are energized.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 22, 2011
    Assignee: CyberOptics Corporation
    Inventors: Lance K. Fisher, Paul R. Haugen
  • Publication number: 20110280468
    Abstract: A system and method for localization and resolvability of an integrated circuit includes selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli are chosen to provide a baseline image and a distinguishing image effect as a result of the chosen stimuli when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set from the one or more electrical stimuli using one or more measurement tools for collecting the baseline image and the distinguishing image effect. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peilin Song, Franco Stellari
  • Patent number: 8057967
    Abstract: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: November 15, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Moshe E. Preil, Xun Chen, Shauh-Teh Juang, James Wiley
  • Patent number: 8055056
    Abstract: In a method of detecting defects of patterns on a semiconductor substrate and an apparatus for performing the method information on positions of reference defects influencing an operation of a circuit including the patterns when the patterns are formed on the semiconductor substrate is acquired in advance. Preliminary defects of the patterns formed on the semiconductor substrate are detected. Positions of the preliminary defects of the patterns are compared with positions of the reference defects. The preliminary defects having the positions substantially the same as the positions of the reference defects are set to be defects of the patterns so that the actual defects are detected.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-An Kim, Yu-Sin Yang, Chung-Sam Jun, Moon-Shik Kang, Ji-Hye Kim
  • Patent number: 8055055
    Abstract: Provided is a foreign matter inspection method for positively detecting a foreign matter in the neighborhood of the edge of a mirror-finished substrate without fail. Edge-emphasis and binarization are performed following the taking of an image of a substrate-under-inspection at a contour of its inspection area, to further detect a plurality of sampling points representative of a contour of the inspection area. An estimated inspection area is determined by determining the size, position and rotation angle of contour lines defined, size-reducibly, from the coordinates of the plurality of sampling points. After applying a mask to the binary image data in an area other than the estimated inspection area, a foreign-matter detection step is performed.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: November 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Taizou Hamada, Tatsutoshi Suenaga
  • Publication number: 20110262028
    Abstract: Method and systems for comparing two images with an image processing system is disclosed. A target image and a selected image are aligned. The selected image is divided into a plurality of image regions, and properties of predetermined regions are combined. A primary image region within the selected image is selected, and a target image region within the target image is selected and properties of the two regions are compared.
    Type: Application
    Filed: July 7, 2011
    Publication date: October 27, 2011
    Applicant: Massachusetts Institute of Technology
    Inventors: Pamela R. Lipson, Pawan Sinha
  • Patent number: 8041103
    Abstract: Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: October 18, 2011
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: Ashok Kulkarni, Brian Duffy, Kais Maayah, Gordon Rouse, Eugene Shifrin
  • Patent number: 8041441
    Abstract: A production management system has processing devices A, B, C, D, E, and P. A kind of product ? is processed in the order of the processing devices A, P, B, P, and C, and a kind of product ? is processed in the order of the processing devices D, P, E, and P. To determine whether the processing device P is to be used to produce the product ? or the product ?, an input ratio of each kind of product is multiplied by the number of times of passing the processing device P for each kind of product, thereby calculating a core of each kind of product. Based on the calculated score, whether the processing device P is to be used to produce the product ? or the product ? is determined. Accordingly, the work-in-process balance of key processes between different kinds of products can be equalized.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: October 18, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Izumi, Katsuhiko Takahashi, Katsumi Morikawa