Abstract: A method of fabrication and device with holes for electrical conduction made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes to form one or more electrical conduction paths on the photosensitive glass substrate, exposing at least one portion of the photosensitive glass substrate to an activating energy source, exposing the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature, cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass-crystalline substrate and etching the glass-crystalline substrate with an etchant solution to form the one or more depressions or through holes for electrical conduction in the device.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: The present disclosure is a method for forming a thin film pattern to form a micron-pattern and a flat display device having the same. The method for forming a thin film pattern includes the steps of forming first to third thin film layers on a substrate in succession, forming a first photoresist pattern on the third thin film layer, patterning the second and third thin film layers using the first photoresist pattern as a mask to form first and second thin film mask pattern having line widths different from each other, forming a second photoresist pattern at a region where the first and second thin film mask patterns do not overlap positioned between the first thin film layer and the second thin film mask pattern, removing the first and second thin film mask patterns, and patterning the first thin film layer using the second photoresist pattern as a mask.

Abstract: A pattern-forming method includes applying a photoresist composition to a substrate to form a resist film. The photoresist composition includes an acid generator and a first polymer that includes an acid-dissociable group. The resist film is exposed. The resist film is developed using a developer having an organic solvent content of 80 mass % or more to form a prepattern of the resist film. A polymer film having a phase separation structure in a space defined by the prepattern is formed using a composition that includes a plurality of second polymers. A part of the phase separation structure of the polymer film is removed.

Abstract: A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.

Abstract: A reverse pattern is formed once by combining a negative exposure mask having a wiring pattern with a positive resist, and then a positive wiring pattern is formed by use of the reverse pattern. That is, a positive resist applied on a semiconductor substrate is exposed by use of the exposure mask having an opening part in a region corresponding to the wiring pattern, and then the exposed part is removed by development to form a resist pattern, thereby forming the wiring pattern in the region corresponding to the opening part of the resist pattern. Consequently, it is hardly affected by flare during EUV exposure, thereby fabricating a fine wiring pattern with higher exposure latitude.

Abstract: There is disclosed A resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), one or more kinds of a compound represented by the following general formula (2), and one or more kinds of a compound, represented by the following general formula (3), and/or an equivalent body thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.

Abstract: A pattern is formed by (1) coating a first positive resist composition onto a substrate, baking, patternwise exposing, PEB, and developing to form a first positive resist pattern including a large area feature, (2) applying a resist-modifying composition comprising a basic nitrogen-containing compound and heating to modify the first resist pattern, and (3) coating a second positive resist composition thereon, patternwise exposing, and developing to form a second resist pattern. The large area feature in the first resist pattern has a film retentivity of at least 50% after the second pattern formation.

Abstract: A method for patterned deposition of an arbitrary thin film on an arbitrary substrate. A GaAs substrate having a bi-layer structure deposited thereon, the bi-layer structure consisting of a bottom layer of Ge and a top layer of SiN. A photoresist deposited on the top SiN surface of the sample is patterned to form one or more desired patterned features on the sample. The Ge—SiN bi-layer structure on the patterned sample is aniostropically etched so that an undercut is formed in the Ge layer, the SiN forming an overhang over a portion of the GaAs substrate. The remaining photoresist is removed from the sample and the film is deposited on the sample to form a feature on the substrate. The remaining Ge layer is etched away and the SiN layer and film deposited on the SiN layer are lifted from the sample, leaving only the patterned features on the substrate.

Abstract: This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices.

Abstract: A method for producing a magnetic recording medium comprising at least a recording layer and a protective film provided on top of a non-magnetic substrate, the method comprising, in the following order, forming a continuous recording layer on the substrate, forming a patterned resist layer, partially removing the recording layer based on a resist pattern, applying an organosilicon compound having an active energy beam-curable functional group onto the recording layer and regions from which the recording layer has been removed, curing the organosilicon compound with an active energy beam, etching the organosilicon compound to expose a magnetic layer, and forming a protective film.

Abstract: A method of forming ceramic pattern structures of silicon carbide film includes depositing an electron-beam resist or a photo-resist onto a substrate. A portion of the resist is selectively removed from the substrate to form a resist pattern on the substrate. A film of pre-ceramic polymer that includes silicon and carbon is deposited onto the substrate and resist pattern and the pre-ceramic polymer film is cured. A portion of the cured pre-ceramic polymer film on the resist pattern is removed, thereby forming a pre-ceramic polymer pattern on the substrate. The pre-ceramic polymer pattern is then converted to a ceramic pattern.

Abstract: A method for fabricating a semiconductor device includes: forming a first photoresist pattern with a first opening over an etch target layer; forming a second photoresist pattern with a plurality of second openings over the first photoresist pattern; and forming a plurality of patterns by etching the etch target layer by using the first photoresist pattern and the second photoresist pattern as an etch barrier.

Abstract: A method includes forming a hard mask layer over an etch target layer that extends across first and second regions, forming a sacrificial layer pattern over the hard mask layer of the first region, removing the sacrificial layer pattern after forming a spacer pattern on side walls thereof, selectively etching the hard mask layer of the first region by using the spacer pattern as an etch barrier while protecting the hard mask layer of the second region from being etched, removing the spacer pattern, forming a cut mask pattern over the hard mask layer of the first and second regions, etching the hard mask layer of the first and second regions by using the cut mask pattern as an etch barrier, removing the cut mask pattern, and forming patterns in the first and second regions respectively by using the hard mask layer of the first and second regions as an etch barrier and etching the etch target layer.

Abstract: The invention relates to a method (3) of fabricating a mold (39, 39?) including the following steps: (a) depositing (9) an electrically conductive layer on the top (20) and bottom (22) of a wafer (21) made of silicon-based material; (b) securing (13) the wafer to a substrate (23) using an adhesive layer; (c) removing (15) one part (26) of the conductive layer from the top of the wafer (21); and (d) etching (17) the wafer as far as the bottom conductive layer (22) thereof in the shape (26) of the one part removed from the top conductive layer (22) to form at least one cavity (25) in the mold. The invention concerns the field of micromechanical parts, particularly, for timepiece movements.

Abstract: A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.

Abstract: The invention concerns a method of fabricating a metallic microstructure, characterized in that it includes the steps consisting in forming a photosensitive resin mold by a LIGA-UV type process, and in the uniform, galvanic deposition of a layer of a first metal and then a layer of a second metal form a block, which approximately reaches the top surface of the photosensitive resin.

Abstract: A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions.

Abstract: A method of manufacturing a semiconductor device using a photolithography process may include forming an anti-reflective layer and a first photoresist film on a lower surface. The first photoresist film may be exposed to light and a first photoresist pattern having a first opening may be formed by developing the first photoresist film. A plasma treatment can be performed on the first photoresist pattern and a second photoresist film may be formed on the first photoresist pattern, which may be exposed to light. A second photoresist pattern may be formed to have a second opening by developing the second photoresist film. Here, the second opening may be substantially narrower than the first opening.

Abstract: Some embodiments include methods in which photolithographically-patterned photoresist features are used as templates during formation of a series of annular structures. The annular structures have linear segments. The linear segments are within a pattern having a pitch which is less than or equal to about half of a pitch of a pattern containing the photoresist features. An expanse of photoresist is formed across the annular structures. The expanse is photolithographically patterned to form chop patterns over ends of the annular structures, and to form at least one opening over at least one of the linear segments. The annular structures are etched while using the patterned photoresist expanse as a mask. In some embodiments, an opening in a photoresist expanse aligns to an edge of a linear segment through scum generated during photolithographic patterning of the photoresist expanse.

Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed,by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: A silsesquioxane-based composition that contains (a) silsesquioxane resins that contain HSiO3/2 units and RSiO3/2 units wherein; R is an acid dissociable group, and (b) 7-diethylamino-4-methylcoumarin. The silsesquioxane-based compositions are useful as positive resist compositions in forming patterned features on substrate, particularly useful for multi-layer layer (i.e. bilayer) 193 nm & 157 nm photolithographic applications.

Abstract: A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: {(SiO1.5—Y—SiO1.5)x(R3SiO1.5)y(XSiO1.5)z}(OH)e(OR6)f??(1).

Abstract: A manufacturing method includes forming a stacked film including first/second/third layers on a substrate, forming a first resist pattern on the stacked film, forming a first film pattern by etching the first layer through the first resist pattern, removing the first resist pattern, partially covering the first film pattern with a second resist pattern, slimming the first film pattern exposed from the second resist pattern, forming a second film pattern by etching the second layer exposed from the first layer through the first film pattern, partially covering the second film pattern with a third resist pattern, removing the first film pattern exposed from the third resist pattern, forming sidewall spacers to the second film pattern and remained second layer, removing the remained second layer portion, followed by etching the third layer through the second film pattern and sidewall spacers to form a third film pattern.

Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

Abstract: There is disclosed a method for forming a resist underlayer film of a multilayer resist film having at least three layers used in a lithography, comprising at least; a step of coating a composition for resist underlayer film containing a novolak resin represented by the following general formula (1) obtained by treating a compound having a bisnaphthol group on a substrate; and a step of curing the coated composition for the resist underlayer film by a heat treatment at a temperature above 300° C. and 600° C. or lower for 10 to 600 seconds. There can be provided a method for forming a resist underlayer film, and a patterning process using the method to form a resist underlayer film in a multilayer resist film having at least three layers used in a lithography, gives a resist underlayer film having a lowered reflectance, a high etching resistance, and a high heat and solvent resistances, especially without wiggling during substrate etching.

Abstract: In a method of manufacturing an organic EL apparatus, a mask layer is formed on an organic compound layer, and a region not covered with the mask layer is patterned by dry etching, in which a charge injection layer is formed using an inorganic compound that has a low etching rate with respect to an etching gas used for patterning of the organic compound layer and that is not decomposed even when exposed to the etching gas.

Abstract: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.

Abstract: A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the mask.

Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.

Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity of metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes being dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance.

Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.

Abstract: An electro-optical printed circuit board contains electrical conductor tracks on the one hand and optical waveguide structures on the other hand. The optical waveguide structures comprise a bottom layer, a core layer and a cladding layer. Visible areas are applied to the printed circuit board, and the core layer is applied later both to the bottom layer as well as the visible areas and structured both on the bottom layer as well as the visible areas. This structure is then transferred to the visible areas, e.g. by etching. Reference marks are thus produced which contain the information on the actual position of the optical waveguide structures.

Abstract: This is structure and method for providing a textured surfaced that can be used in a plurality of systems including ink jet printing. In ink jet printing, the textured surface of this invention controls ink drawback and significantly improves image quality. The textured surface has an average roughness, Ra, of about 0.2 to 1.5 microns, a texture density of about 104-107 pits per cm2, a texture size of about 0.5-5 microns, and a texture depth of about 0.5-10 microns.

Abstract: The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.

Abstract: Alignment tolerances between narrow mask lines and wider mask lines in an integrated circuit are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. The narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, a shadowing effect causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction.

Abstract: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

Abstract: A method and system for providing a PMR pole in a magnetic recording transducer including an intermediate layer are disclosed. The method and system include providing a mask on the intermediate layer. The mask includes a line having at least one side. A hard mask layer is provided on the mask. At least a portion of the hard mask layer resides on the side(s) of the line. At least part of the hard mask layer on the side(s) of the line is removed. Thus, at least a portion of the line is exposed. The line is then removed, providing an aperture in the hard mask corresponding to the line. The method also includes forming a trench in the intermediate layer under the aperture. The trench top is wider than its bottom. The method further includes providing a PMR pole, at least a portion of which resides in the trench.

Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.

Abstract: A solid-state imaging device producing method includes the steps of: applying a resist material onto a substrate in which a channel region is formed; forming a resist layer by exposure and development of the resist material using a mask, the resist layer having an opening and a thin-film portion, the mask having a first region through which light is transmitted and a second region through which a smaller quantity of light than that the light transmitted through the first region is transmitted; subjecting the substrate to ion implantation using the resist layer as a mask to form an impurity region; etching the substrate using the resist layer as a mask after the ion implantation to form an alignment mark; and forming an electrode on the impurity region and part of the channel region using the alignment mark as a reference.

Abstract: A composition comprising (A) a fluorinated polymer having k=0.01-0.4 and n=1.4-2.1 and (B) an aromatic ring-bearing polymer having k=0.3-1.2 is used to form an antireflective coating. The ARC-forming composition can be deposited by the same process as prior art ARCs. The resulting ARC is effective in preventing reflection of exposure light in photolithography and has an acceptable dry etching rate.

Abstract: A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer.

Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.

Abstract: A system and method include forming an optical cavity by positioning a photonic crystal a predetermined distance from a substrate, and creating, within the cavity, a standing wave having a substantially flat wavefront. The standing wave may be created by applying an input wave to a first surface of the photonic crystal. The predetermined distance may be such that a peak intensity of the standing wave is proximate to or a calculated distance from the substrate surface. The peak intensity may vary in relation to the substrate surface. The method may include tuning the peak intensity location within the cavity by shifting the wavelength of the input wave or altering the characteristics of the photonic crystal by an external field. A second photonic crystal may be used on the other side of the substrate to replace the reflecting properties of the substrate, allowing for further smoothing of the wavefront.

Abstract: A patterning method is provided. First, a material layer is formed on a substrate. Thereafter, an ashable layer is formed on the material layer. Afterwards, a patterned transfer layer is formed on the ashable layer, wherein the patterned transfer layer has a critical dimension less than the exposure limit dimension. Further, the ashable layer is patterned using the patterned transfer layer or a complementary layer of the patterned transfer layer as a mask, so as to form a patterned ashable layer. The material layer is then patterned using the patterned ashable layer as a mask.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.

Abstract: A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.