Etching Of Substrate And Material Deposition Patents (Class 430/314)
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Patent number: 8294034Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.Type: GrantFiled: May 28, 2010Date of Patent: October 23, 2012Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Patent number: 8288082Abstract: Example embodiments provide a method of fabricating a triode-structure field-emission device. A cathode, an insulating layer, and a gate metal layer may be sequentially formed on a substrate. A first resist pattern having a first opening and a second resist pattern having a second opening smaller than the first opening may be formed to be sequentially laminated on the gate metal layer. Then, the gate metal layer and the insulating layer may be etched using the first resist pattern to form a gate electrode and an insulating layer having a first hole and a second hole corresponding to the first opening. A catalyst layer may be formed on the cathode exposed through the first and second holes using the second resist pattern. After the first resist pattern, second resist pattern, and the catalyst layer on the second resist pattern are removed, an emitter may be formed on the catalyst layer in the second hole.Type: GrantFiled: November 10, 2008Date of Patent: October 16, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chan Wook Baik, Junhee Choi, Seog Woo Hong, Joo Ho Lee
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Patent number: 8283253Abstract: A pattern forming method for forming a pattern serving as a mask, includes a process for forming a first pattern 105, a process for trimming a width of the first pattern 105, a process for forming a boundary layer 106 on a surface of the first pattern 105, a process for forming a second mask material layer 107 on a surface of the boundary layer 106, a process for removing a part of the second mask material layer 107 to expose top portions of the boundary layer 106, and a process for exposing the first pattern 105 and forming a second pattern having the second mask material layer 107 at a top portion thereof by etching the boundary layer 106.Type: GrantFiled: February 13, 2009Date of Patent: October 9, 2012Assignee: Tokyo Electron LimitedInventors: Hidetami Yaegashi, Satoru Shimura, Takashi Hayakawa
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Patent number: 8283256Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.Type: GrantFiled: February 24, 2011Date of Patent: October 9, 2012Assignee: Integrated Device Technology inc.Inventors: Wanling Pan, Harmeet Bhugra
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Patent number: 8273522Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.Type: GrantFiled: November 15, 2011Date of Patent: September 25, 2012Assignee: Hynix Semiconductor Inc.Inventors: Joo Kyoung Song, Hyoung Soon Yune
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Patent number: 8273661Abstract: Provided is a pattern forming method for forming a pattern serving as a mask, which includes: a process for forming a first pattern 105 made of a photoresist; a process for forming a boundary layer 106 at sidewall portions and top portions of the first pattern 105; a process for forming a second mask material layer 107 to cover a surface of the boundary layer 106; a process for removing a part of the second mask material layer 107 to expose top portions of the boundary layer 106; a process for forming a second pattern made of the second mask material layer 107 by etching and removing the boundary layer 106; and a trimming process for reducing a width of the first pattern 105 and a width of the second pattern to predetermined widths.Type: GrantFiled: February 13, 2009Date of Patent: September 25, 2012Assignee: Tokyo Electron LimitedInventors: Hidetami Yaegashi, Satoru Shimura
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Patent number: 8268532Abstract: The invention relates to a method for forming microscopic structures. By scanning a focused particle beam over a substrate in the presence of a precursor fluid, a patterned seed layer is formed. By now growing this layer with Atomic Layer Deposition or Chemical Vapor Deposition, a high quality layer can be grown. An advantage of this method is that forming the seed layer takes relatively little time, as only a very thin layer needs to be deposited.Type: GrantFiled: December 18, 2009Date of Patent: September 18, 2012Assignee: FEI CompanyInventors: Alan Frank De Jong, Johannes Jacobus Lambertus Mulders, Wilhelmus Mathijs Marie Kessels, Adriaan Jacobus Martinus Mackus
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Patent number: 8257909Abstract: The present invention provides a method of manufacturing a semiconductor device capable of highly detailed patterning using a resist pattern having smoothed wall surfaces and reduced roughness. The method includes the steps of: forming a resist pattern over a base layer; applying a resist pattern smoothing material onto a surface of the resist pattern, thereafter heating and developing; and etching the base layer using the smoothed resist pattern, wherein one of an application thickness and a heat temperature is adjusted so as to smooth at least wall surfaces of the resist pattern. Aspects in which a maximum opening dimension and a minimum opening dimension of the smoothed resist pattern are ±5% of a predetermined opening dimension D (nm), and an average opening dimension Dav. (nm) of the smoothed resist pattern satisfies Dav. (nm)?D (nm)×(90/100), are preferable.Type: GrantFiled: August 26, 2003Date of Patent: September 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Hajime Yamamoto, Satoshi Takechi
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Patent number: 8252506Abstract: Hot melt compositions include acid waxes and acrylate functional monomers free of acid groups. Upon application of actinic radiation, the hot melt compositions cure to form and etch resist. The hot melt compositions may be used in the manufacture of printed circuit boards, optoelectronic and photovoltaic devices.Type: GrantFiled: November 4, 2009Date of Patent: August 28, 2012Assignee: Rohm and Haas Electronic Materials LLCInventors: Kevin J. Cheetham, Thomas C. Sutter
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Patent number: 8252151Abstract: In a layout method of a bridging electrode, the method includes the steps of: providing a substrate; forming a transparent electro-conductive layer on the substrate and the transparent electro-conductive layer having a plurality of neighboring patterned blocks; forming an alignment film layer on the substrate and the alignment film layer having a plurality of bridging grooves of a bridging insulation unit crossing between the patterned blocks; forming an electro-conductive layer on the substrate and the electro-conductive layer having a plurality of wires respectively disposed on the bridging grooves, wherein the wires of the electro-conductive layer being formed through an optical compensation mask in conjunction with at least one of over-exposure and over-development; and forming a protection layer on the substrate to enhance optical transmission and to protect the substrate, the transparent electro-conductive layer, the alignment film layer and the electro-conductive layer.Type: GrantFiled: March 24, 2010Date of Patent: August 28, 2012Inventor: Li-Li Fan
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Patent number: 8252491Abstract: A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has a larger pitch than the pattern. Finally, one of the two feature types is selectively etched in the open areas. The result is a marker with a large pitch suitable to be read with long wavelength radiation but the edges of the features are defined in an exposure step having a pitch comparable to the product features.Type: GrantFiled: November 17, 2009Date of Patent: August 28, 2012Assignee: ASML Netherlands B.V.Inventors: Richard Johannes Franciscus Van Haren, Maurits Van Der Schaar
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Patent number: 8241838Abstract: A method of manufacturing a semiconductor device includes the following processes. A first resist layer covering an etching object is patterned to form a first resist pattern. Then, a filling layer that covers the first resist pattern and has a flat upper surface is formed. Then, a second resist layer covering the flat upper surface is patterned to from a second resist pattern.Type: GrantFiled: August 21, 2009Date of Patent: August 14, 2012Assignee: Elpida Memory, Inc.Inventor: Hiroshi Yoshino
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Patent number: 8241823Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.Type: GrantFiled: September 29, 2011Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
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Publication number: 20120193762Abstract: A novel reversal lithography process without etch back is described. The reversal material comprises nanoparticles that are selectively deposited into the gaps between features without overcoating the tops of the features. As a result, a patterned imaging layer can be removed using solvent, blanket exposure followed by developer washing, or dry etching directly, without an etch-back process, and the original bright field lithography pattern can be reversed into dark field features, and transferred into subsequent layers using the nanoparticle reversal material as an etch mask.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: BREWER SCIENCE INC.Inventors: Qin Lin, Daniel M. Sullivan, Hao Xu, Tony D. Flaim
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Patent number: 8227173Abstract: A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.Type: GrantFiled: June 2, 2008Date of Patent: July 24, 2012Assignee: Samsung Techwin Co., Ltd.Inventor: Jae-chul Ryu
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Patent number: 8227175Abstract: A method for smoothing a printed circuit board (PCB), comprising: providing a PCB having a first smooth outer surface and an opposite second outer surface, the second outer surface including a smooth region and a plurality of dimples; applying a liquid photoresist layer onto the second outer surface of the PCB to fill the dimples; solidifying the liquid photoresist in the dimples to obtain a solidified photoresist layer; polishing the solidified photoresist layer until a surface thereof being coplanar with the smooth region; and polishing the entire second outer surface until the solidified photoresist layer is removed, thereby obtaining a plain outer surface parallel to the first smooth outer surface.Type: GrantFiled: May 17, 2009Date of Patent: July 24, 2012Assignee: Zhen Ding Technology Co., Ltd.Inventors: Chung-Jen Tsai, Yu-Cheng Huang, Hung-Yi Chang, Cheng-Hsien Lin
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Patent number: 8222075Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.Type: GrantFiled: March 17, 2009Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Eiji Ito
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Patent number: 8222152Abstract: A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.Type: GrantFiled: May 5, 2010Date of Patent: July 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jun-Hyeub Sun
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Publication number: 20120168210Abstract: A method for forming a conductive contact includes forming a copper contact region in an intermediary layer, depositing an insulator layer over the copper contact region and the intermediary layer, patterning a photoresist layer on the insulator layer, etching to remove a portion of the insulator layer and expose a portion of the copper contact region, depositing a conductive material layer over the exposed portion of the copper contact region and the photoresist layer, and removing the photoresist layer and the conductive material layer disposed on the photoresist layer.Type: ApplicationFiled: January 5, 2011Publication date: July 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Vidhya Ramachandran
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Publication number: 20120168203Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventor: Ravi Prakash Srivastava
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Patent number: 8207576Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: January 31, 2007Date of Patent: June 26, 2012Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Patent number: 8198017Abstract: A producing method of a wired circuit board includes the steps of preparing a two-layer base material including a metal supporting layer and an insulating layer, covering an upper surface of the insulating layer and respective side end surfaces of the insulating layer and the metal supporting layer with a photoresist, placing a photomask so as to light-shield an end portion and a portion where a conductive layer is to be formed of the upper surface, exposing to light the photoresist covering the upper surface from above the photoresist via the photomask, exposing to light the photoresist covering the respective side end surfaces from below the photoresist, forming an exposed portion of the photoresist into a pattern by removing an unexposed portion thereof to form a plating resist, and forming an end-portion conductive layer and the conductive layer.Type: GrantFiled: January 22, 2009Date of Patent: June 12, 2012Assignee: Nitto Denko CorporationInventor: Keiji Takemura
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Patent number: 8198016Abstract: The present invention provides a patterning process, in which a resistance with regard to an organic solvent used for a composition for formation of a reverse film is rendered to a positive pattern to the degree of necessity and yet solubility into an alkaline etching liquid is secured, thereby enabling to finally obtain a negative image by a positive-negative reversal by performing a wet etching using an alkaline etching liquid. A resist patterning process of the present invention using a positive-negative reversal comprises at least a step of forming a resist film by applying a positive resist composition; a step of obtaining a positive pattern by exposing and developing the resist film; a step of crosslinking the positive resist pattern thus obtained; a step of forming a reverse film; and a step of reversing the positive pattern to a negative pattern by dissolving into an alkaline wet-etching liquid for removal.Type: GrantFiled: May 4, 2009Date of Patent: June 12, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Tsutomu Ogihara, Mutsuo Nakashima, Kazuhiro Katayama
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Patent number: 8192921Abstract: A pattern is formed by coating a chemically amplified positive resist composition comprising a resin comprising acid labile group-containing recurring units and a photoacid generator onto a substrate, drying to form a resist film, exposing the resist film to high-energy radiation through a phase shift mask having a lattice-like array of shifters, PEB, developing to form a positive pattern, illuminating or heating the positive pattern to eliminate acid labile groups for increasing alkaline solubility and to induce crosslinking for imparting solvent resistance, coating a reversal film, and dissolving away the positive pattern in an alkaline wet etchant to form a pattern by way of positive/negative reversal.Type: GrantFiled: January 13, 2010Date of Patent: June 5, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Takao Yoshihara, Kazuhiro Katayama
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Patent number: 8187788Abstract: Disclosed is a photosensitive resin composition comprising an alkali-soluble resin, wherein the dissolution rate of the alkali-soluble resin in an aqueous sodium carbonate solution is not less than 0.04 ?m/sec. When a photosensitive layer having a thickness of 30 ?m is formed by applying the photosensitive resin composition onto a base and removing the solvent by heating, and thus-obtained photosensitive layer is irradiated with an active ray of 1000 mJ/cm2 or less, the dissolution rate of the portion irradiated with the active ray in the photosensitive layer made of the photosensitive resin composition is not less than 0.22 ?m/sec and the film residual rate of the portion not irradiated with the active ray is not less than 90%.Type: GrantFiled: April 24, 2007Date of Patent: May 29, 2012Assignee: Asahi Kasei Kabushiki KaishaInventors: Kuon Miyazaki, Takashi Hayakawa
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Patent number: 8182978Abstract: Compositions characterized by the presence of an aqueous base-soluble polymer having aromatic moieties and aliphatic alcohol moieties have been found which are especially useful as developable bottom antireflective coatings in 193 nm lithographic processes. The compositions enable improved lithographic processes which are especially useful in the context of subsequent ion implantation or other similar processes where avoidance of aggressive antireflective coating removal techniques is desired.Type: GrantFiled: February 2, 2009Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Wu-Song Huang, Libor Vyklicky, Pushkara Rao Varanasi
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Publication number: 20120121983Abstract: The present invention relates to a lithium deposited anode for a lithium secondary battery and a method for preparing the same, and more particularly, to an anode suitable for a lithium secondary battery which limits dendrite growth only inside the concave portion of the silicon substrate during a battery is charged/discharged by depositing lithium as an active material only on the deeply caved concave portion of an anode current collector of which a micro-size patterned silicon substrate has conductivity provided by a metal, and its manufacturing method.Type: ApplicationFiled: April 11, 2011Publication date: May 17, 2012Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Woo-Young Yoon, Heon Lee, Dae-Gun Jin
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Patent number: 8178405Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.Type: GrantFiled: April 7, 2010Date of Patent: May 15, 2012Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
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Patent number: 8178286Abstract: A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern comprising a first grid, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, where the second photoresist pattern is a second grid which overlaps the first grid to form a photoresist web, and etching the underlying layer using the photoresist web as a mask.Type: GrantFiled: June 8, 2011Date of Patent: May 15, 2012Assignee: SanDisk 3D LLCInventor: Michael Chan
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Publication number: 20120103507Abstract: Disclosed herein is a method for manufacturing a circuit board. The method for manufacturing a circuit board includes: preparing a photosensitive composite; preparing a build-up insulating film by casting the photosensitive composite into a film made of poly ethylene terephthalate (PET) material; stacking the build-up insulation film on the board; forming via holes on the build-up insulation film by using a photolithography process; and forming conductive vias in the via holes.Type: ApplicationFiled: September 21, 2011Publication date: May 3, 2012Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae Choon Cho, Hyung Mi Jung, Hwa Young Lee, Choon Keun Lee
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Patent number: 8168374Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.Type: GrantFiled: August 12, 2010Date of Patent: May 1, 2012Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Jiunn-Hsiung Liao
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Patent number: 8163466Abstract: A method forms a first patterned mask (comprising rectangular features and/or rounded openings) on a planar surface and forms a second patterned mask on the first patterned mask and the planar surface. The second patterned mask covers protected portions of the first patterned mask and the second patterned mask reveals exposed portions of the first patterned mask. The method treats the exposed portions of the first patterned mask with a chemical treatment that reduces the size of the exposed portions to create an altered first patterned mask.Type: GrantFiled: February 17, 2009Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Kuang-Jung Chen, Wai-Kin Li
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Patent number: 8158334Abstract: An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.Type: GrantFiled: January 14, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Allen H. Gabor, Scott D. Halle, Helen Wang
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Patent number: 8158332Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a first resist pattern made of a first resist material on a workpiece material; irradiating an energy beam onto the first resist pattern, the energy beam exposing the first resist material to light; performing a treatment for improving resistance the first resist pattern after irradiation of the energy beam; forming a coating film on the workpiece material so as to cover the first resist pattern; and forming a second resist pattern made of a second resist material on the coating film after the treatment.Type: GrantFiled: January 19, 2010Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara
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Patent number: 8158333Abstract: A manufacturing method includes forming a stacked film including first/second/third layers on a substrate, forming a first resist pattern on the stacked film, forming a first film pattern by etching the first layer through the first resist pattern, removing the first resist pattern, partially covering the first film pattern with a second resist pattern, slimming the first film pattern exposed from the second resist pattern, forming a second film pattern by etching the second layer exposed from the first layer through the first film pattern, partially covering the second film pattern with a third resist pattern, removing the first film pattern exposed from the third resist pattern, forming sidewall spacers to the second film pattern and remained second layer, removing the remained second layer portion, followed by etching the third layer through the second film pattern and sidewall spacers to form a third film pattern.Type: GrantFiled: March 27, 2007Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Koji Hashimoto
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Patent number: 8143533Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.Type: GrantFiled: May 17, 2006Date of Patent: March 27, 2012Assignees: Mitsubishi Paper Mills Limited, Shinko Electric Industries Co., Ltd.Inventors: Yasuo Kaneda, Munetoshi Irisawa, Yuji Toyoda, Toyokazu Komuro, Katsuya Fukase, Toyoaki Sakai
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Patent number: 8142250Abstract: A method of forming a color filter touch sensing substrate integrates touch-sensing structures/elements of a touch panel into the inner side of the color filter substrate, which faces a thin film transistor substrate, and forms patterned assistant electrodes on the surfaces of the transparent sensing pads for decreasing the equivalent resistance of the touch-sensing structures/elements. Moreover, since an adjacent transparent conductive layer and an assistant electrode layer are patterned to form the transparent sensing pads and the patterned assistant electrodes, a simplified pattern-transferring process can be applied to the transparent sensing pads and the patterned assistant electrodes, or bridge structures can be formed from the assistant electrode layer for electrically connecting between some transparent sensing pads. Therefore, the forming process is simplified.Type: GrantFiled: September 27, 2011Date of Patent: March 27, 2012Assignee: AU Optronics Corp.Inventors: Yu-Feng Chien, Chau-Shiang Huang, Tun-Chun Yang, Seok-Lyul Lee
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Patent number: 8129094Abstract: A spacer is formed on side and top portions of a photoresist pattern after a mask process is performed so that the spacer may be used as an etching mask. The spacer is formed using a polymer deposition layer which is a low temperature oxide or nitride that can be deposited on side and top portions of the photoresist pattern at 75˜220° C. after the mask process is performed. A method for manufacturing a semiconductor device includes forming a bottom anti-reflection coating film on an etch-target layer, patterning a photoresist layer formed on the bottom anti-reflection coating film, forming an insulation layer on a patterned photoresist layer and the bottom anti-reflection coating film, etching back the insulation layer to form a spacer on sidewalls of the patterned photoresist layer, and etching the bottom anti-reflection coating film and the etching target layer exposed by the spacer to form a fine pattern.Type: GrantFiled: June 27, 2008Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Ki Lyoung Lee
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Patent number: 8129095Abstract: A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity of metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes being dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance.Type: GrantFiled: November 20, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Casey Jon Grant, Jude L. Hankey
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Patent number: 8124323Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: September 25, 2007Date of Patent: February 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
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Publication number: 20120044187Abstract: One embodiment in accordance with the invention can include a capacitive touch screen. The capacitive touch screen includes a substantially transparent substrate and a plurality of electrodes formed on the substantially transparent substrate. The plurality of electrodes are substantially parallel in a first direction and each of the plurality of electrodes includes a layer of light altering material.Type: ApplicationFiled: March 29, 2009Publication date: February 23, 2012Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Igor Polishchuk, Edward Grivna
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Patent number: 8119324Abstract: A pattern formation method suitable for forming micro-patterns using electron beams (EB), X-rays, or extreme ultraviolet radiation (EUV) is provided.Type: GrantFiled: July 27, 2007Date of Patent: February 21, 2012Assignee: JSR CorporationInventors: Hikaru Sugita, Nobuji Matsumura, Daisuke Shimizu, Toshiyuki Kai, Tsutomu Shimokawa
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Patent number: 8119334Abstract: Negative photoresist over an insulating layer is exposed to radiation according to a pattern for an opening in the insulating layer for filling conductive material. A post of the negative photoresist is left over the location where the opening in the insulating layer is to be formed. A developable hard mask is formed over the post by a spin-on process so that the hard mask over the post is much thinner than directly over the insulating layer. An etch back is performed to remove the hard mask from over the post so that the post of negative photoresist is thus exposed. The post is removed to form an opening in the hard mask. An etch is performed to form the opening in the insulating layer aligned to the opening in the hard mask. The opening in the insulating layer is filled with the conductive material.Type: GrantFiled: April 30, 2008Date of Patent: February 21, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Willard E. Conley
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Patent number: 8110322Abstract: The invention provides a method for forming a selective mask on a surface of a layer of AlXGaYIn1-X-YAsZP1-Z or AlXGaYIn1-X-YNZAs1-Z (0?X?1, 0?Y?1, 0?Z?1), which is a method for forming a mask with a minute width suitable for microfabrication in nano-order. (1) An energy beam 4a, 4b is selectively irradiated onto a natural oxide layer 2 formed on the surface of the layer 1 of AlXGaYIn1-X-YAsZP1-Z or AlXGaYIn1-X-YNZAs1-Z. (2) Of the natural oxide layer 2, parts other than parts onto which the energy beam 4a, 4b has been irradiated is removed by heating. (3) The natural oxide layer 2 of the parts onto which the energy beam 4a, 4b has been irradiated is partially removed by heating while alternatively carrying out a rise and fall in heating temperature.Type: GrantFiled: April 25, 2005Date of Patent: February 7, 2012Assignee: RiberInventors: Naokatsu Sano, Tadaaki Kaneko
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Patent number: 8101481Abstract: A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the like. In one embodiment, a process is provided for fabricating a 6-transistor Static Random-Access Memory (SRAM) cell or arrays of 6-transistor SRAM cells using only, or at least primarily, positive and negative spacer lithography.Type: GrantFiled: February 25, 2008Date of Patent: January 24, 2012Assignee: The Regents of the University of CaliforniaInventor: Andrew E. Carlson
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Patent number: 8101341Abstract: A pattern is formed by coating a chemically amplified positive resist composition comprising a resin comprising acid labile group-containing recurring units and a photoacid generator onto a substrate, drying to form a resist film, exposing the resist film to high-energy radiation, PEB, developing to form a positive pattern, illuminating or heating the positive pattern to eliminate acid labile groups for increasing alkaline solubility and to induce crosslinking for imparting solvent resistance, coating a reversal film, forming a space pattern, and shrinking the space pattern.Type: GrantFiled: January 13, 2010Date of Patent: January 24, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Kazuhiro Katayama
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Patent number: 8097401Abstract: A composition of matter. The composition of matter includes a polymer having an ethylenic backbone and comprising a first monomer having an aromatic moiety, a second monomer having a base soluble moiety or an acid labile protected base soluble moiety, and a third monomer having a fluoroalkyl moiety. Also a photoresist formulation including the composition of matter and a method of imaging using the photoresist formulation including the composition of matter.Type: GrantFiled: March 24, 2009Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Wu-Song Huang, Irene Popova, Pushkara Rao Varanasi, Libor Vyklicky
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Patent number: 8084185Abstract: The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking. The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.Type: GrantFiled: January 8, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Sean D. Burns, Colin J. Brodsky, Ryan L. Burns
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Patent number: 8084191Abstract: A thermoelectric module and method of manufacture thereof, capable of preventing short-circuits between electrodes due to solder without causing increases in size or cost. A thermoelectric module is configured with lower electrodes formed on the inside surface of a lower substrate, placed in opposition to an upper substrate, on the inside surface of which are formed upper electrodes; the end faces of thermoelectric elements are soldered to the lower electrodes and upper electrodes. Each of the electrodes is configured from three layers, which are a copper layer, a nickel layer formed on one face of the copper layer, and a gold layer formed on one face of the nickel layer; a visor portion, protruding outward, is formed in the nickel layer, so that when positioning the thermoelectric elements above the electrodes and soldering the electrodes to the thermoelectric elements, the flowing of solder 18a from the side portions of electrodes to the insulating substrate is prevented.Type: GrantFiled: October 15, 2009Date of Patent: December 27, 2011Assignee: Japan CorporationInventor: Hidetoshi Yasutake
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Patent number: 8080366Abstract: An in-line process for making a thin film electronic device on a substrate is described comprising the steps of: a) depositing a structurable layer onto a substrate; b) depositing a patternable material onto the structurable layer in a first pattern; and c) etching the structurable layer in areas uncovered by the patternable material. The steps are carried out without intermediate exposure of the substrate to ambient air.Type: GrantFiled: February 23, 2007Date of Patent: December 20, 2011Assignee: OTB Solar B.V.Inventors: Ronaldus Joannes Cornelis Maria Kok, Marinus Franciscus Johannes Evers, Franciscus Cornelius Dings