Post Imaging Radiant Energy Exposure Patents (Class 430/328)
  • Patent number: 8465903
    Abstract: Methods for forming photoresists sensitive to radiation on a substrate are provided. Described are chemical vapor deposition methods of forming films (e.g., silicon-containing films) as photoresists using a plasma which may be exposed to radiation to form a pattern. The deposition methods utilize precursors with cross-linkable moieties that will cross-link upon exposure to radiation. Radiation may be carried out in the with or without the presence of oxygen. Exposed or unexposed areas may then be developed in an aqueous base developer.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: June 18, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weidman, Timothy Michaelson, Paul Deaton, Nitin K. Ingle, Abhijit Basu Mallick, Amit Chatterjee
  • Patent number: 8460857
    Abstract: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara
  • Patent number: 8445183
    Abstract: A method of manufacturing a semiconductor device, includes: a first resist film formation process of forming a first resist film on a processing target surface using a positive-type photoresist material; a first resist pattern formation process of forming a first resist pattern by performing development after exposure in which light is irradiated onto the first resist film; a second resist film formation process of forming a second resist film on the processing target surface, where the first resist pattern is formed, using a photoresist material; and a second resist pattern formation process of forming a second resist pattern by performing exposure in which light is irradiated onto the second resist film and then performing development. The method further includes an insolubilization process for insolubilizing the first resist pattern against a developer and a solvent of a photoresist material used in the second resist pattern formation process.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 21, 2013
    Assignee: Sony Corporation
    Inventor: Hiroyuki Miyamoto
  • Patent number: 8435728
    Abstract: A method and system for patterning a substrate using a radiation-sensitive material is described. The method and system include forming a layer of radiation-sensitive material on a substrate, exposing the layer of radiation-sensitive material to a pattern of radiation, and then performing a post-exposure bake following the exposing. The imaged layer of radiation-sensitive material is then developed to remove either a region having high radiation exposure or a region having low radiation exposure to form radiation-sensitive material lines. An exposure gradient within the radiation-sensitive material lines is then removed, followed by slimming the radiation-sensitive material lines.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 7, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Benjamin M. Rathsack, Mark H. Somervell
  • Patent number: 8426113
    Abstract: The present invention provides chemically amplified silsesquioxane polymers for preparing masks using e-beam lithography. The silsesquioxane polymers have reactive sidechains that in the presence of an acid undergo acid catalyzed rearrangement to generate reactive functionalities that crosslink to form Si—O—Si bonds. The reactive side-chains comprise ?- and ?-substituted alkyl groups bound to the silicon of the silsesquioxane polymer. The substituent of the ?- and ?-substituted alkyl group is an electron withdrawing group. Resists generated with the chemically amplified silsesquioxane polymers of the present invention and imaged with e-beams have resolution of ?60 nm line/space.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Luisa Dominica Bozano, Blake W. Davis, Alshakim Nelson, Jitendra Singh Rathore, Linda Karin Sundberg
  • Patent number: 8420302
    Abstract: A method of fine patterning a thin film and a method of manufacturing a display substrate by using the same, in which a fine photo pattern is formed on a base substrate, and a photoresist pattern is formed on the thin film. A fine photo pattern is formed by ashing the photoresist pattern. A fine pattern is formed by removing the thin film exposing through the fine photo pattern. A fine pattern is formed, and the fine pattern has a higher resolution than that of an exposure apparatus. The reliability of a process for manufacturing a display substrate and the display quality of a display device may be improved.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: April 16, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoon-Sung Um, Su-Jeong Kim, Hye-Ran You, Jae-Jin Lyu, Seung-Beom Park
  • Patent number: 8404407
    Abstract: According to certain embodiments, a mask blank for an electron beam writing is provided, capable of forming a resist pattern of a 3-dimensional topology through an one-time writing. The mask blank includes a substrate, a thin film formed on the substrate, and an electron beam resist film formed on the thin film. The electron beam resist film is made of a laminated film including at least a lower resist film and an upper resist film. The lower resist film and the upper resist film have different resist sensitivities with respect to an electron beam.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: March 26, 2013
    Assignee: Hoya Corporation
    Inventors: Masahiro Hashimoto, Hiroshi Shirotori, Yuusuke Honma, Mitsuhiro Shirakura
  • Patent number: 8394720
    Abstract: A plasma processing method includes modifying a resist pattern of the substrate; and trimming the modified resist pattern through a plasma etching. The modifying includes: supplying the processing gas for modification from the processing gas supply unit to the inside of the processing chamber while the substrate having a surface on which the resist pattern is formed is mounted on the lower electrode; supplying the high frequency power from the high frequency power supply to generate a plasma of the processing gas for modification; and supplying the negative DC voltage from the DC power supply to the upper electrode.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 12, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Jin Fujihara
  • Patent number: 8361699
    Abstract: The present invention relates to a method for performing high speed electron beam lithography (EBL). An electron beam source (EBS), capable of emitting an electron beam towards the energy sensitive resist, forms a first pattern (P1) on the substrate, the first pattern defining a first direction (D1) on the substrate. The electron beam source then forms a second pattern (P2) on the substrate. The energy and/or dose delivered to the energy sensitive resist during the exposure of the first and the second pattern is dimensioned so that the threshold dose/energy of the energy sensitive resist is reached on the overlapping portions of the first and the second patterns (P1, P2). The invention provides a high speed technique for the production of substrates with high quality developed patterns, e.g. hole or dot arrays, by electron beam lithography. Each hole or dot may be defined by the mutually overlapping portions of the first and second pattern, e.g.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: January 29, 2013
    Assignee: Nil Technology APS
    Inventors: Theodor Kamp Nielsen, Brian Bilenberg, Peixiong Shi
  • Patent number: 8329381
    Abstract: A pattern forming method includes providing a first mask with a first aperture, forming a first transfer pattern on a resist by irradiating a first electron beam through the first aperture, the first transfer pattern extending in a first direction and having a boundary along a circumference thereof, and the first electron beam having a cross section of a first square when emerging from the first aperture, and forming a second transfer pattern on the resist by irradiating a second electron beam through the first aperture, the second transfer pattern extending in the first direction and overlapping a portion the boundary of the first transfer pattern, and the second electron beam having a cross section of a second square when emerging from the first aperture.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Byung-Gook Kim, Hee-Bom Kim, Sang-Hee Lee
  • Patent number: 8329366
    Abstract: A method is described for alignment of a substrate during a double patterning process. A first resist layer containing at least one alignment mark is formed on the substrate. After the first resist layer is developed, a second resist layer is deposited over the first resist layer, leaving a planar top surface (i.e., without topography). By baking the second resist layer appropriately, a symmetric alignment mark is formed in the second resist layer with little or no offset error from the alignment mark in the first resist layer. The symmetry of the alignment mark formed in the second resist can be enhanced by appropriate adjustments of the respective thicknesses of the first and second resist layers, the coating process parameters, and the baking process parameters.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: December 11, 2012
    Assignees: ASML Netherlands B.V., ASML Holding N.V.
    Inventors: Maya Angelova Doytcheva, Mircea Dusa, Richard Johannes Franciscus Van Haren, Harry Sewell, Robertus Wilhelmus Van Der Heijden
  • Patent number: 8318407
    Abstract: Devices having a thin film or laminate structure comprising hafnium and/or zirconium oxy hydroxy compounds, and methods for making such devices, are disclosed. The hafnium and zirconium compounds can be doped, typically with other metals, such as lanthanum. Examples of electronic devices or components that can be made include, without limitation, insulators, transistors and capacitors. A method for patterning a device using the materials as positive or negative resists or as functional device components also is described. For example, a master plate for imprint lithography can be made. An embodiment of a method for making a device having a corrosion barrier also is described. Embodiments of an optical device comprising an optical substrate and coating also are described. Embodiments of a physical ruler also are disclosed, such as for accurately measuring dimensions using an electron microscope.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 27, 2012
    Assignee: State of Oregon acting by and through the State Board of Higher Education on behalf of Oregon State University
    Inventors: Douglas A. Keszler, Jeremy Anderson, Peter A. Hersh, Jason K. Stowers
  • Patent number: 8298732
    Abstract: An exposure method includes generating a reticle exposure pattern based on a target pattern, performing a lithography simulation based on the reticle exposure pattern to generate a simulation pattern that simulates a resist pattern formed by reticle exposure, generating differential data between the target pattern and the simulation pattern, generating a first electron-beam exposure pattern based on the differential data, generating a reticle based on the reticle exposure pattern, performing an optical exposure process with respect to a resist by use of the reticle, and performing an electron-beam exposure process with respect to the resist based on the first electron-beam exposure pattern.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 30, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiko Minemura, Seiji Makino, Kanji Takeuchi, Noboru Sugiyama, Kozo Ogino
  • Patent number: 8278026
    Abstract: A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 2, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Gaobo Xu
  • Patent number: 8263315
    Abstract: A pattern-forming method includes selectively exposing a resist layer formed using a positive-tone radiation-sensitive resin composition including a resin component and an acid generator. The resist layer is developed to form a first pattern. An uncrosslinked embedded section is formed adjacent the first the pattern using a pattern-forming resin composition including a polymer. The polymer has a carbon content higher than that of the resin component, does not include silicon atom in a molecule, and is crosslinkable due to an acid generated from the acid generator. The uncrosslinked embedded section is crosslinked in an area around an interface with the first pattern to form an array structure. The first pattern, a first crosslinked section, the uncrosslinked embedded section, and a second crosslinked section are repeatedly arranged in the array structure in this order. The first pattern and the uncrosslinked embedded section are removed to form a second pattern.
    Type: Grant
    Filed: June 13, 2010
    Date of Patent: September 11, 2012
    Assignee: JSR Corporation
    Inventor: Keiji Konno
  • Patent number: 8241841
    Abstract: The present invention provides a process for producing a surface-modified layer system comprising a substrate (2) and a self-assembled monolayer (SAM) (1) anchored to its surface. The SAM (1) is comprised by aryl or rigid alicyclic moiety species. The process comprises providing a polymorphic SAM (1) anchored to the substrate (2), and thermally treating (4) the SAM to change from a first to a second structural form thereof. The invention also provides a thermolithographic form of process in which the thermal treatment (4) is used to transfer a pattern (3) to the SAM (1), which is then developed.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: August 14, 2012
    Assignee: The University Court of the University of St. Andrews
    Inventors: Manfred Buck, Piotr Cyganik
  • Patent number: 8236484
    Abstract: As the critical dimensions of liftoff patterns grow smaller, it becomes increasingly more difficult to make liftoff resists that have the required resolution. This problem has been overcome by use of a combination of ion beam processing and ozone slimming to form lift-off patterns with undercuts from a single layer of photoresist. The ion beam process serves to harden the top portion of the resist while the ozone is used to oxidize and erode the lower portion resist sidewall to form the undercut.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: August 7, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Jei-Wei Chang, Chao-Peng Chen, Chunping Luo, Shou-Chen Kao
  • Patent number: 8211619
    Abstract: The present invention provides: a positive photosensitive composition that yields an insulation layer superior not only in high transparency, but also in heat resistance enduring a temperature during the production of a substrate, solvent resistance, and anti-aging property as a permanent resist; a positive permanent resist utilizing the positive photosensitive composition; and a method for producing the positive permanent resist. The present invention provides: a positive photosensitive composition containing (A) a curable silicone resin having a silanol group, which resin has a structure obtained by a reaction between one or more cyclic siloxane compounds represented by the following general formula (1): and one or more arylalkoxysilane compounds represented by the following general formula (2): (B) diazonaphthoquinones, and (C) a solvent; a positive permanent resist using the positive photosensitive composition; and a method for producing the positive permanent resist.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: July 3, 2012
    Assignee: Adeka Corporation
    Inventors: Hiroshi Morita, Hiromi Sato, Atsushi Kobayashi, Jinichi Omi, Seiichi Saito
  • Patent number: 8197996
    Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 12, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 8198016
    Abstract: The present invention provides a patterning process, in which a resistance with regard to an organic solvent used for a composition for formation of a reverse film is rendered to a positive pattern to the degree of necessity and yet solubility into an alkaline etching liquid is secured, thereby enabling to finally obtain a negative image by a positive-negative reversal by performing a wet etching using an alkaline etching liquid. A resist patterning process of the present invention using a positive-negative reversal comprises at least a step of forming a resist film by applying a positive resist composition; a step of obtaining a positive pattern by exposing and developing the resist film; a step of crosslinking the positive resist pattern thus obtained; a step of forming a reverse film; and a step of reversing the positive pattern to a negative pattern by dissolving into an alkaline wet-etching liquid for removal.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: June 12, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Tsutomu Ogihara, Mutsuo Nakashima, Kazuhiro Katayama
  • Patent number: 8187795
    Abstract: Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods utilized herein allow for efficient manufacture of large area (e.g., up to 1 mm2 or greater or 1 m2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques described herein further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described herein are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 29, 2012
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Kanti Jain, Kevin Lin
  • Patent number: 8158332
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a first resist pattern made of a first resist material on a workpiece material; irradiating an energy beam onto the first resist pattern, the energy beam exposing the first resist material to light; performing a treatment for improving resistance the first resist pattern after irradiation of the energy beam; forming a coating film on the workpiece material so as to cover the first resist pattern; and forming a second resist pattern made of a second resist material on the coating film after the treatment.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara
  • Patent number: 8158312
    Abstract: A charged particle beam exposure method that includes preparing of exposure data for a plurality of device patterns; obtaining of an integral of forward scattering components in an exposure intensity distribution with each of the device patterns near the center of the exposure intensity distribution as domain of integration; correcting of the shape of each of the plurality of device patterns by correcting the exposure data, so that the integral is equal to a reference value; and appropriating of mask patterns within an exposure mask to each of the device patterns following the correction, such that the center of gravity of each of the device patterns matches the center of gravity of the mask pattern appropriated thereto.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kozo Ogino
  • Patent number: 8148052
    Abstract: A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 3, 2012
    Assignee: NXP B.V.
    Inventors: Anja Monique Vanleenhove, Peter Dirksen, David Van Steenwinckel, Gerben Doornbos, Casper Juffermans, Mark Van Dal
  • Patent number: 8129080
    Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: March 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 8124326
    Abstract: A method of patterning positive photoresist includes providing positive photoresist over a substrate. An area of the positive photoresist is exposed to a pattern of activating radiation at a dose which is below the Dose To CD of the pattern with the positive photoresist. The area of the positive photoresist is flood exposed to activating radiation at a dose from 1% to 75% of E0. A sum of the flood dose and the pattern dose is less than the Dose To CD yet effective to resolve the pattern in the positive photoresist upon develop. After exposing the area to the flood dose and the pattern dose, the area of the positive photoresist is developed to resolve the pattern in the positive photoresist. Other embodiments are contemplated.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Paul D. Shirley, Hiroyuki Mori
  • Patent number: 8124319
    Abstract: A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: February 28, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Pei-Lin Huang, Chun-Yen Huang, Yi-Ming Wang
  • Patent number: 8110325
    Abstract: A substrate treatment method including a first treatment process (S13 to S16) for exposing, heating, and developing a substrate on which a first resist is formed, thereby forming a first resist pattern, and a second treatment process (S17 to S20) for forming a second resist film on the substrate on which the first resist pattern is formed, exposing, heating, and developing the substrate on which the second resist film is formed, thereby forming a second resist pattern. Also, the substrate treatment method compensates a first treatment condition in a first treatment process (S22 to S25) based on a measured value of a line width of the second resist pattern and a second treatment condition in a second treatment process (S26 to S29) based on a measured value of a line width of the first resist pattern.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: February 7, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Takafumi Niwa, Hiroshi Nakamura, Hideharu Kyouda
  • Patent number: 8110322
    Abstract: The invention provides a method for forming a selective mask on a surface of a layer of AlXGaYIn1-X-YAsZP1-Z or AlXGaYIn1-X-YNZAs1-Z (0?X?1, 0?Y?1, 0?Z?1), which is a method for forming a mask with a minute width suitable for microfabrication in nano-order. (1) An energy beam 4a, 4b is selectively irradiated onto a natural oxide layer 2 formed on the surface of the layer 1 of AlXGaYIn1-X-YAsZP1-Z or AlXGaYIn1-X-YNZAs1-Z. (2) Of the natural oxide layer 2, parts other than parts onto which the energy beam 4a, 4b has been irradiated is removed by heating. (3) The natural oxide layer 2 of the parts onto which the energy beam 4a, 4b has been irradiated is partially removed by heating while alternatively carrying out a rise and fall in heating temperature.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: February 7, 2012
    Assignee: Riber
    Inventors: Naokatsu Sano, Tadaaki Kaneko
  • Patent number: 8105764
    Abstract: A pattern is formed through positive/negative reversal by coating a chemically amplified positive resist composition comprising an acid labile group-bearing resin, a photoacid generator, and an organic solvent onto a substrate, prebaking the resist composition, exposing the resist film to high-energy radiation, post-exposure heating, and developing the exposed resist film with an alkaline developer to form a positive pattern; irradiating or heating the positive pattern to facilitate elimination of acid labile groups and crosslinking for improving alkali solubility and imparting solvent resistance; coating a reversal film-forming composition thereon to form a reversal film; and applying an alkaline wet etchant thereto for dissolving away the positive pattern.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: January 31, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Takao Yoshihara, Toshinobu Ishihara
  • Patent number: 8053172
    Abstract: Photolithography compositions and methods. A first layer of a first photoresist is formed on a substrate. A second layer of a second photoresist is formed directly onto the first layer. The second polymer of the second photoresist includes an absorbing moiety. The second layer is patternwise imaged and developed, resulting in removal of base-soluble regions. A relief pattern from the second layer remains. The relief pattern and the first layer are exposed to a second dose of the radiation. The polymer in the relief pattern absorbs a portion of the second dose. A fraction of the second dose passes through the at least one region of the relief pattern and exposes at least one region of the first layer. The relief pattern and base-soluble regions of the first layer are removed. A relief pattern from the first layer remains. A second photolithography method and a photoresist composition are also included.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Scott David Halle, Wu-Song Huang, Ranee Wai-Ling Kwong, Pushkara R. Varanasi
  • Patent number: 8053174
    Abstract: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara
  • Patent number: 8029971
    Abstract: Compositions, a method, and a photopatternable blend. The compositions include a blend of a first and a second polymer. The first polymer is a substituted silsesquioxane copolymer. The second polymer is a substituted silsesquioxane polymer. The second polymer is configured to undergo chemical crosslinking with the first polymer, the second polymer, or a combination thereof, upon exposure to light, thermal energy, or a combination thereof. The compositions include a photosensitive acid generator. The method includes forming a film. The film is patternwise imaged, and at least one region is exposed to radiation. After the imaging, the film is baked, wherein at least one exposed region is rendered substantially soluble. After the baking, the film is developed, wherein a relief pattern remains. The relief pattern is exposed to radiation. The relief pattern is baked. The relief pattern is cured. A chemically amplified positive-tone photopatternable blend is also described.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Allen, Phillip Joe Brock, Blake W. Davis, Qinghuang Lin, Robert D. Miller, Alshakim Nelson, Ratnam Sooriyakumaran
  • Patent number: 8026045
    Abstract: A conductor circuit (2) having a predetermined pattern is formed on a base material (1); a photosensitive resin composition layer is formed on a surface of the base material, on which the conductor circuit (2) having the predetermined pattern is formed, by using a photosensitive resin composition; a surface of the photosensitive resin composition layer is irradiated with and exposed to active light rays through a photomask having a predetermined pattern; a solder resist layer (3a) having a predetermined pattern is formed by using a developing solution; and the formed solder resist layer (3a) is irradiated with ultraviolet light by using a low-pressure mercury-vapor lamp.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 27, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Masaki Mizutani, Hirofumi Fujii
  • Patent number: 8012675
    Abstract: A method of patterning a target layer on a substrate is described. A patterned photoresist layer is formed over the target layer, wherein the patterned photoresist layer has unexposed parts as separate islands and each unexposed part has a low proton concentration at least in its sidewalls. Acid-crosslinked polymer layers are formed only on the sidewalls of each unexposed part. A flood exposure step is performed to the substrate. A baking step is performed to the patterned photoresist layer. A development step is performed to remove the previously unexposed parts. The target layer is etched with the acid-crosslinked polymer layers as a mask.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: September 6, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Publication number: 20110194092
    Abstract: A target for measuring an overlay error or a critical dimension of a substrate comprises a grating. In one example, lines of the grating are arranged at an angle of about 45° with respect to edges of the target.
    Type: Application
    Filed: July 9, 2009
    Publication date: August 11, 2011
    Applicant: ASML Netherlands B.V.
    Inventors: Hendrik Jan Hidde Smilde, Willem Marie Julia Marcel Coene
  • Patent number: 7977019
    Abstract: A semiconductor device manufacturing method, a semiconductor device manufacturing equipment and a computer readable medium storing a computer program provide for easily identifying a cause of a deviation of pattern dimensions from the objective dimension. A first storage section stores a relation between a PEB temperature and a photoresist dimension of a post-lithography. A second storage section stores a relation between a PEB temperature and a post-etching dimension. A primary correction section determines a first corrected PEB temperature for conforming the photoresist dimension of a post-lithography to the objective dimension, using the relation data stored in the first storage section. A secondary correction section determines the second corrected PEB temperature for conforming the post-etching dimension using the first corrected PEB temperature to the objective dimension, using the relation data stored in the second storage section.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Murakami
  • Patent number: 7972755
    Abstract: There is disclosed a substrate processing method by a multi-patterning technique, which comprises a lithography process and an etching process, each of the processes is performed to one substrate at least twice. The substrate processing method is performed by using a substrate processing system comprising a plurality of process units for performing respective steps of the lithography process. When a second lithography process is performed to a substrate, process unit(s) for performing one or more steps of the second lithography process to be used in the second lithography process is automatically selected based on the process history of the first lithography process in such a way that the process unit(s) to be used in the second lithography process is (are) identical to the processed unit(s) used in the first lithography process.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: July 5, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Yuichi Yamamoto
  • Patent number: 7968273
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Nanosys, Inc.
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri L. Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 7943286
    Abstract: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 17, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Dong Xu, Gabriel Cueva, Pane-chane Chao, Wendell Kong
  • Patent number: 7939241
    Abstract: The present invention relates to a novel (meth)acrylamide compound represented by the general formula (1), a (co)polymer of the (meth)acrylamide compound, and a chemically amplified photosensitive resin composition composed of the polymer and a photoacid generator. In the formula, R1 represents a hydrogen atom or a methyl group; R2 represents an acid-decomposable group; and R3 to R6 independently represent a hydrogen atom, a halogen atom or an alkyl group having 1 to 4 carbon atoms.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 10, 2011
    Assignee: NEC Corporation
    Inventors: Katsumi Maeda, Kaichirou Nakano
  • Patent number: 7906271
    Abstract: The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning lithography process. The method comprises receiving data describing a drawn pattern. A first photomask pattern is formed for implementing a region of the drawn pattern on the substrate. A second photomask pattern is formed comprising one or more pattern features having longitudinal edges for implementing the region of the drawn pattern on the substrate, wherein at least 90% of all the longitudinal edges of the second photomask pattern that are positioned within the region are oriented in substantially the same direction. Both a system for forming the photomask patterns and a process for patterning a device using the photomask patterns are also disclosed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas J. Aton
  • Patent number: 7875409
    Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinroku Maejima, Seiichiro Shirai, Takahiro Machida
  • Patent number: 7875419
    Abstract: It is an object to provide a technique for removing a resist favorably without leaving residue in the case of using a nonaqueous resist stripper. According to the present invention, in order to achieve the object, when a resist pattern is removed by using the nonaqueous resist stripper, it becomes easier to remove the resist pattern after dry etching or ion doping, by performing exposure treatment on the resist pattern. After a resist pattern is formed from a DNQ-novolac resin type of positive resist composition, the resist pattern is irradiated with light within the range of photosensitive wavelength of the DNQ photosensitizer, thereby removing the resist pattern with the nonaqueous resist stripper.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaharu Nagai, Kiyofumi Ogino, Teruhisa Nakai, Eiji Shioda
  • Patent number: 7867689
    Abstract: A method. The method includes dip coating a film of a composition on a silicon wafer substrate. The composition includes a polymer blend of a first polymer and a second polymer. The first polymer is a substituted silsesquioxane copolymer. The second polymer is a polysilsesquioxane having silanol end groups. The composition includes a photosensitive acid generator, an organic base, and an organic crosslinking agent. The film is patternwise imaged and at least one region is exposed to radiation having a wavelength of about 248 nanometers. The film is baked, resulting in inducing crosslinking in the film. The film is developed resulting in removal of base-soluble unexposed regions of the film, wherein a relief pattern from the film remains. The relief pattern is cured at a temperature between about 300° C. and about 450° C., and the curing utilizes a combination of thermal treatment with UV radiation.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Allen, Phillip Brock, Blake W. Davis, Qinghuang Lin, Robert D. Miller, Alshakim Nelson, Ratnam Sooriyakumaran
  • Patent number: 7862965
    Abstract: A method for detecting defects which originate from a chemical solution includes coating a chemical solution on a surface of a mask, and radiating an exposure beam to the mask on which the chemical solution is coated, thereby performing enlarged projection exposure on a resist film which is formed on a surface of a substrate for an inspection. Further, the method for detecting defects which originate from a chemical solution includes performing an inspection of defects on the resist film which has been subjected to the enlarged projection exposure, and determining whether a result of the inspection meets a predetermined standard.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisako Aoyama, Yuji Kobayashi
  • Patent number: 7851136
    Abstract: An integrated circuit fabrication process as described herein employs a photoresist stabilization step where patterned photoresist material is exposed to radiation having a wavelength that promotes cross-linking in the shallow surfaces of the patterned photoresist features. The patterned photoresist material is highly absorptive of the stabilizing radiation, which results in the surface cross-linking and modification of the outer surfaces of the patterned photoresist material. This modified “shell” is immune to photoresist developer, photoresist solvents, intense ion implantation, and intense etchants. The shell also enables for the resist not to deform when baked at a temperature above its glass transition temperature. For example, the photoresist stabilization technique can be used in a double exposure process such that a patterned photoresist layer remains intact during a subsequent lithographic sub-process.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 14, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Harry J. Levinson, Ryoung-han Kim, Thomas I. Wallow
  • Patent number: 7829269
    Abstract: A method and system for patterning a substrate using a dual tone development process is described. The method comprises use of plural photo-acid generators with or without a flood exposure of the substrate to improve process latitude for the dual tone development process.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: November 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer, Wallace P. Printz
  • Patent number: 7799515
    Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaharu Nagai, Ichiro Uehara
  • Patent number: 7759660
    Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are also disclosed.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 20, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Baorui Yang