Abstract: A method of sorting dies found on wafers is disclosed. Each wafer is part of a set of wafers and the sorting rejects some of the dies. The method first selects an acceptable deviation within an abstract distribution. A respective test parameter is measured and recorded for each die in the set of wafers, and a distribution of the test parameter across the set of wafers is calculated. Based on this distribution and the acceptable deviation, a test parameter limit is set and any dies having a test parameter value greater than the limit are rejected.

Abstract: A variety of test structures may be fabricated with aluminum runners and overlying dielectrics. The dielectrics are removed and bumps are observed upon the aluminum runners. Unevenness in the bump distribution is a predictor of long term reliability problems. A test structure may be utilized to design integrated mass production fabrication processes.

Abstract: The ESD circuit of the present invention comprises a protection device, and output circuitry. The ESD circuitry illustratively comprises an NMOS and PMOS transistor and two protective diodes. However, in place of the NMOS and PMOS transistors, any two-terminal protection device may be used. The protection device of the present invention comprises the diodes of the ESD circuitry. These diodes are formed within the seal-ring structure of an IC. The seal-ring structure is formed using the following steps. First, a field oxide is grown. N.sup.+ and P.sup.+ impurities are diffused into the substrate. An insulating layer is then grown over the oxide, P.sup.+, and N.sup.+ regions. The insulating layer is etched back, uncovering the substrate, P.sup.+ region, and a portion of the N.sup.+ region. Similarly, a thick aluminum layer is deposited and etched back to form a first connection layer. Subsequently, an insulating layer is formed over the first insulating layer.

Abstract: The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Abstract: Techniques for improving manufacturing process control based on inspection of manufactured items at intermediate process steps, based on clustering and binning of defect data. Additionally, the using the defect data produced by inspection machines to improve manufacturing process control specifically relating to semiconductor manufacturing process control. Examples described here relate specifically to semiconductor wafers, but may be generalized to any manufacturing process.

Abstract: A method for testing a bumped semiconductor die (14) is accomplished without excessively deforming the conductive bumps (200). In one form, testing is accomplished using a test contactor (12) which includes a deformable layer (204), such as an elastomer, which is patterned to include a plurality of openings (202) corresponding in pattern to the conductive bumps (200). The die is positioned next to the test contactor and the two are compressed together. The walls of the openings in the elastomeric material constrain the deformation of the conductive bumps in the X-Y plane due to the lateral pressure exerted on the sides of the conductive bumps. In a second form, a mechanical standoff (216) limits the extent to which the die and the test contactor can approach, thereby limiting the deformation in the Z-axis. In a third form, both elastomeric material and mechanical standoff act to constrain the deformation in the X-, Y-, and Z- axes.

Abstract: An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic identification information. The integrated circuit also includes an optical identification mark displaying a machine-readable optical identification code which corresponds with the electronic identification information stored in the identification circuit. The data encoded in the optical identification code may be identical with that of the electronic identification information. Alternatively, a look-up table or other correlating means may be employed to associate the optical identification code with the electronic identification information. The integrated circuit is packaged in a housing, and another optical identification mark is placed on an external surface of the housing.

Abstract: A silicon substance is etched by using alkaline etchant containing additive (Cu, Pb, Mg). The content of the additive is controlled intentionally to provide desired etching quality during an etching operation.

Abstract: In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Abstract: A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static measurement method, to determine capacitance-voltage characteristics at the area of hemispherical grain polysilicon.

Abstract: Apparatus controls a wafer potential in a plasma system when the plasma is off to keep the wafer slightly negative at all times in order to reduce and eliminate the collection of charged particles on the wafer. The apparatus allows the wafer bias to be reduced to a small negative voltage and then holds that voltage. This greatly reduces the net positive flux to the wafer. A diode and a programmed power supply hold a minimum negative voltage on the back of the wafer electrode when the plasma density is decaying to zero.

Abstract: The invention is carried out in a plasma reactor for processing a semiconductor wafer, the plasma reactor having a chamber for containing a processing gas and having a conductor connected to an RF power source for coupling RF power into the reactor chamber to generate from the processing gas a plasma inside the chamber, the chamber containing at least one surface exposed toward the plasma and susceptible to contamination by particles produced during processing of the wafer, the invention being carried out by promoting, during processing of the wafer, bombarding of particles from the plasma onto the one surface to remove therefrom contaminants deposited during processing of the wafer. Such promoting of bombarding is carried out by providing an RF power supply and coupling, during processing of the wafer, RF power from the supply to the one surface. The coupling may be performed by a capacitive cleaning electrode adjacent the one surface, the capacitive cleaning electrode connected to the RF power supply.

Abstract: The breakdown of an ultra-thin dielectric layer is detected by applying a test signal to the layer. Measurements are taken of noise signals present in the layer during the application of the test signal. At breakdown, a significant increase occurs in the amplitude of the measured noise signals.

Abstract: An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers.

Abstract: An interface apparatus located between a chamber unit and a stepper main controller, which collectively constitute a stepper adapted to form a pattern film on a semiconductor substrate by using a photolithography process well-known in the art. The interface is adapted to detect and control abnormal operational states within the chamber unit via a main controller on the main stepper unit even if the main stepper unit and the chamber unit are made by different manufacturers.

Abstract: In a method and an apparatus for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer, is measured, and then stored in a memory means together with data of the position of each semiconductor integrated circuit. The plurality of semiconductor integrated circuits on the wafer are cut into individual semiconductor integrated circuit chips.

Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.

Abstract: In a semiconductor strain sensor, for example, using resistors of a polycrystalline semiconductor material such as polycrystalline silicon as strain gauges, the sum of the temperature coefficient of resistance (TCR) of the resistor and the temperature coefficient of strain sensitivity (TCK) is adjusted not by controlling the impurity carrier concentration but by controlling the resistivity, thereby an output fluctuation due to a change in the temperature can be suppressed.