Abstract: A method of performing a thermal process using a bake plate of a track lithography tool. The bake plate includes a plurality of heater zones. The method includes providing a first drive signal to a first electrode in electrical communication with a process surface of the bake plate. The first electrode is associated with a first heater zone of the plurality of heater zones and each of the plurality of heater zones is adapted to receive a control voltage. The method also includes moving a semiconductor substrate toward the process surface of the bake plate, receiving a first response signal from the first electrode, processing the first response signal to determine a first capacitance value associated with a first gap between the first electrode and a first portion of the semiconductor substrate, and providing a measurement signal related to the first capacitance value.

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract: A device and method for determining target values for a parameter of a semiconductor device to be trimmed.

Abstract: By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.

Abstract: A method for fabricating semiconductor wafers using physical vapor deposition. The method includes maintaining a substrate on a susceptor in a chamber. The substrate has a face positioned within a vicinity of a target material, which is within the chamber. The target member comprises a first side and a second side. Preferably, the first side is positioned toward the face of the substrate. The method includes operating a magnet device fixed about a rotating member, which is coupled to the chamber and is coupled to a drive motor, which is coupled to a driver. A magnet device is positioned from a center region of the rotating member by a predetermined dimension. The method includes moving the magnet device in an annular manner about the center region using the rotating member. The magnet device is rotated at a velocity v and influences a spatial region, which is positioned overlying the second side of the target.

Abstract: In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

Abstract: A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which repeatability of an apparatus control can be secured. The invention has been finalized focusing on the result. That is, if plasma irradiation starts, a dose is initially increased, but a time at which the dose is made substantially uniform without depending on a time variation is continued. In addition, if the time is further increased, the dose is decreased. The dose can be accurately controlled through a process window of the time at which the dose is made substantially uniform without depending on the time variation.

Abstract: Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.

Abstract: A method for etching a dielectric film is provided herein. In accordance with the method, a device (201) is provided which comprises a first chamber (203) equipped with a first gas supply (209) and a second chamber (205) equipped with a second gas supply (215), wherein the second chamber is in communication with the first chamber by way of an acceleration grid (211) having a variable potential. The gas flow into the plasma chamber is oscillated between a first state in which the gas flow into the first chamber has the composition f11 and the gas flow into the second chamber has the composition f21, and a second state in which the gas flow into the first chamber has the composition f12 and the gas flow into the second chamber has the composition f22.

Abstract: A MOSFET has its gate voltage controlled to provide a constant drain current of the MOSFET, for example to limit inrush current for charging a capacitance of a power supply arrangement. A decrease in the gate voltage supplied to the MOSFET, corresponding to an increase in the junction temperature of the MOSFET, by more than a determined amount is detected and used to reduce the gate voltage, and hence the drain current, for example to zero, to prevent heating of the MOSFET beyond a maximum operating temperature.

Abstract: A new method to form an image sensor device is achieved. The method comprises forming an image sensing array in a substrate comprising a plurality of light detecting diodes with spaces between the diodes. A first dielectric layer is formed overlying the diodes but not the spaces. The first dielectric layer has a first refractive index. A second dielectric layer is formed overlying the spaces but not the diodes. The second dielectric layer has a second refractive index that is larger than the first refractive index. A new image sensor device is disclosed.

Abstract: A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised features. The sidewall material is selected to have a different atomic number and is preferably an nonconductive such as silicon dioxide or alumina. After the nonconductive material deposition, a controlled directional RIE process is used to remove the insulator layer deposited on the top and bottom surface of the lines and trenches. The remaining voids between the sidewalls of the raised features are filled with a conductive material. The wafer is then planarized with chemical mechanical planarization (CMP) to expose the nonconductive sidewall material on the surface. The nonconductive sidewall material will be fine lines embedded in conductive material.

Abstract: The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at least one characteristic parameter associated with at least one device structure on the at least one workpiece. The method also includes comparing the at least one characteristic parameter associated with the at least one non-device structure and the at least one characteristic parameter associated with at least one device structure.

Abstract: A plasma processor chamber includes a bottom electrode and a top electrode assembly having a center electrode surrounded by a grounded electrode. RF excited plasma between the electrodes induces a DC bias on them. A measure of the bottom electrode DC bias controls the capacitance of a first series resonant circuit connected between the center electrode and ground. A measure of the center electrode DC bias controls the capacitance of a second series resonant circuit connected between the bottom electrode and ground.

Abstract: A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the solid state membrane, and a nanopore penetrating an area of the conductive material and at least a portion of the solid state membrane. During fabrication a conductive material is applied on a portion of a solid state membrane surface, and a nanopore of a first diameter is formed. When the surface is exposed to an ion beam, material from the membrane and conductive material flows to reduce the diameter of the nanopore. A method for evaluating a polymer molecule using the solid state nanopore device is also described. The device is contacted with the polymer molecule and the molecule is passed through the nanopore, allowing each monomer of the polymer molecule to be monitored.

Abstract: A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.

Abstract: It is an object of the present invention to provide a method of manufacturing a display device, which can display images favorably by insulating a short-circuit portion between an anode and a cathode. Further, it is another object of the invention to provide a method of manufacturing a display device, which can prevent intrusion of moisture so as to inhibit deterioration of a light emitting element when the short-circuit portion between the anode and the cathode is insulated. Specifically, the invention provide a method of manufacturing a display device, wherein a reverse bias voltage is applied to the light emitting element including an electro-luminescent material between the anode and the cathode so as to insulate the short-circuit portion between the anode and the cathode at a temperature of from ?40° C. to 8° C., more preferably, from ?25° C. to 8° C.

Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.

Abstract: A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.

Abstract: The present invention is generally directed to various methods for determining the reliability of dielectric layers. In one illustrative embodiment, the method comprises providing a device having a dielectric layer, applying a plurality of constant voltage pulses to the device and measuring a current through the dielectric layer after one or more of the constant voltage pulses has been applied.

Abstract: A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to the wafer, performing a thermal treatment process, removing the barrier layer, and measuring a physical property of the wafer. The measured physical property of the wafer can be used to ascertain the status of the ion implanter. For instance, the measured physical property can be used to determine whether the ion implanter has problems when the energy or concentration of the implanted ions is changed.

Abstract: There is provided by this invention a wafer probe for measuring plasma and surface characteristics in plasma processing environment that utilizes integrated sensors on a wafer substrate. A microprocessor mounted on the substrate receives input signals from the integrated sensors to process, store, and transmit the data. A wireless communication transceiver receives the data from the microprocessor and transmits information outside of the plasma processing system to a computer that collects the data during plasma processing. The integrated sensors may be dual floating Langmuir probes, temperature measuring devices, resonant beam gas sensors, or hall magnetic sensors. There is also provided a self-contained power source that utilizes the plasma for power that is comprised of a topographically dependent charging device or a charging structure that utilizes stacked capacitors.

Abstract: Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.

Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.

Abstract: A property of a layer is measured by: (1) focusing a heating beam on a region (also called “heated region”) of a conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at any time the temperature of an optically absorbing layer is approximately equal to (e.g., within 90% of) a temperature of the optically absorbing layer when heated by an unmodulated beam, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit area) of a conductive pad formed by patterning the conductive layer. Change in measurement across regions indicates a corresponding change in resistance of the layer.

Abstract: A semiconductor device fabrication method comprises; a first step S1 of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively; a second step S4 of making a probe test on the plural semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of the plural semiconductor wafers; and the third step S5 of computing a yield of the plural semiconductor chips present in the sampling region, when the yields of the plural semiconductor chips computed in the third step are a reference value or above, the probe test is not made on the plural semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of the plural semiconductor wafers fabricated in the same lot as said one semiconductor wafer.

Abstract: In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of corresponding lot is for an etching process after a predetermined RF time of etching apparatus. RF time of the etching apparatus is compared with the predetermined RF time, and it is decided whether the etching process of corresponding lot can be performed in the etching apparatus if the etching process for the corresponding lot should be performed after a lapse of the predetermined RF time.

Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.

Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.

Abstract: A method and system of controlling a process from run-to-run for semiconductor manufacturing. The method of control utilizes a process model to establish a relationship between process control input data and process control output data. The method of control involves minimizing the difference between target process control output data and process control output data predicted by applying the process model to the new process control input data.

Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding the core die and at least one additional die from the die cluster to a weighted character map, and assigning a weighting value to each of the dice added to the weighted character map. At least one tier of buffer dice is then added to the weighted character map adjacent to each die on the weighted character map. Both the dice from the die cluster and the tier of buffer dice are marked, thereby preventing those dice from being packaged and consequently, shipped to customers.

Abstract: The present invention, referred to as optoelectronic probe, concerns a novel apparatus and method for characterization and micromanipulation of particles or biomolecules in an electrolyte solution. Electric fields, which include both time constant and time-varying components, are applied to a thin insulating layer covered, lightly doped semiconductor material. Illumination injects carriers into the insulator/semiconductor interface to compensate the leaking minority carrier current and maintain an inversion layer, which works as an electrode to control the particle movements. A particle array, or even a single cell, can be assembled in, or moved along with the inversion layer electrode, which is induced by illumination. Furthermore, an impedance analyzer is utilized to characterize the trapped particles, or single cell. The present invention has numerous uses, such as bio-chemical analysis systems, and nanosize structures assembly for electronic or optical devices.

Abstract: Defect analysis of a semiconductor die is enhanced in a manner that makes possible the viewing of spatial manifestations of the defect from virtually any angle. According to an example embodiment of the present invention, substrate is removed from a semiconductor die while simultaneously obtaining images of the portions of the die from which substrate is being removed. The images are taken at various points in the substrate removal process, recorded and combined together to form a three-dimensional image of selected portions of the die. The image is then used to view the selected portions, and the nature of one or more defects therein are analyzed.

Abstract: A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

Abstract: A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a hold capacitor having a first electrode formed from the first structural material and a second electrode formed from the second structural material, where the testing method comprises a first step for applying a first voltage to the hold capacitor; a second step for applying a second voltage to the hold capacitor after the first step; a third step for measuring the charge in the pixel after applying the second voltage; and a fourth step for calculating the capacitance of the hold capacitor from the charge and the potential difference between the first voltage and the second voltage.

Abstract: A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of the RTA process. The RTA process comprises steps of proceeding a first RTA step to a wafer in the RTA equipment, then comparing a measured value of the operation parameter with a reference range of value of the operation parameter, thereafter proceeding a second RTA step to the wafer in the RTA equipment when the measured value of the operation parameter is in between the reference range of value of the operation parameter. When the measured value of the operation parameter is out of the reference range of value of the operation parameter, the RTA equipment is turned off, and the wafer is unloaded from the RTA equipment and loaded into another RTA equipment to complete the RTA process.

Abstract: A chemical mechanical polishing apparatus has a polishing pad, a carrier to hold a substrate against a first side of the polishing surface, and a motor coupled to at least one of the polishing pad and carrier head for generating relative motion therebetween. An eddy current monitoring system is positioned to generate an alternating magnetic field in proximity to the substrate, an optical monitoring system generates a light beam and detects reflections of the light beam from the substrate, and a controller receives signals from the eddy current monitoring system and the optical monitoring system.

Abstract: A micro-transfer device for fine positioning is employed typically in recording and playback apparatus for recording disks. Voltage is stably supplied to an expandable element which displaces the position of a recording head by applying voltage. An end different from one end connected to a base, where the recording head is mounted, is fixed to a fixing substrate for preventing changes in dimensions of the expandable element. An external electrode connection for supplying voltage to the expandable element is provided in an area on the fixing substrate.

Abstract: A capacitance probe for thin dielectric film characterization provides a highly sensitive capacitance measurement method and reduces the contact area needed to obtain such a measurement. Preferably, the capacitance probe is connected to a measurement system by a transmission line and comprises a center conductive tip and RLC components between the center conductor and the ground of the transmission line. When the probe tip is in contact with a sample, an MIS or MIM structure is formed, with the RLC components and the capacitance of the MIS or MIM structure forming a resonant circuit. By sending a driving signal to the probe and measuring the reflected signal from the probe through the transmission line, the resonant characteristic of the resonant circuit can be obtained. The capacitance of the MIS or MIM structure is obtainable from the resonant characteristics and the dielectric film thickness or other dielectric properties are also extractable.

Abstract: A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate.

Abstract: A method is provided, the method comprising sampling at least one parameter characteristic of processing performed on a workpiece in at least one processing step, and modeling the at least one characteristic parameter sampled using an adaptive sampling processing model, treating sampling as an integrated part of a dynamic control environment, varying the sampling based upon at least one of situational information, upstream events and requirements of run-to-run controllers. The method also comprises applying the adaptive sampling processing model to modify the processing performed in the at least one processing step.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: A cutting instrument including a metal blade has a recess formed therein and a semiconductor substrate affixed to the blade in the recess. The semiconductor substrate includes at least one sensor formed thereon. The sensor formed on the semiconductor substrate may comprise at least one or an array of a strain sensors, pressure sensors, nerve sensors, temperature sensors, density sensors, accelerometers, and gyroscopes. The cutting instrument may also further include a handle wherein the blade is affixed to the handle and the semiconductor substrate is electrically coupled to the handle. The handle may then be coupled, either physically or by wireless transmission, to a computer that is adapted to display information to a person using the cutting instrument based on signals generated by one or more of the sensors formed on the semiconductor substrate. The computer or handle may also be adapted to store data based on the signals generated by one or more of the sensors.

Abstract: A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The system includes a reticle test system that is capable of applying a voltage to the probe points, measuring the resulting current, calculating the corresponding resistance of the test features, and determining the critical dimensions of the test features. The system is also capable of determining defects based on the resistance measurements. The critical dimension information and defect information can then be used to refine the processes used in the fabrication of subsequent reticles.

Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: The present invention is generally directed to fault detection and control methodologies for ion implant processes, and a system for performing same. In one illustrative embodiment, the method comprises performing a tuning process for an ion implant tool, the tuning process resulting in at least one tool parameter for the ion implant tool, selecting or creating a fault detection model for an ion implant process to be performed in the ion implant tool based upon the tool parameter resulting from the tuning process, and monitoring an ion implant process performed in the ion implant tool using the selected or created fault detection model.

Abstract: An apparatus and method thereof includes at least one acoustic transducer for receiving acoustic emissions produced during a semiconductor fabrication process. The acoustic transducer is mounted to various mechanical components of a semiconductor processing equipment in a manner so that the acoustic transducer receives acoustic emissions produced during the fabrication process. The received acoustic emissions are analyzed in in-situ to identify and determine surface characteristics of the wafer.