Abstract: A test key and a method for monitoring a semiconductor wafer are disclosed. The test key includes a first testing unit and a second testing unit. The first testing unit has a first diode-to-conductive layer area ratio. The second testing unit has a second diode-to-conductive layer area ratio. The second diode-to-conductive layer area ratio is smaller than the first diode-to-conductive layer area ratio.

Abstract: A virtual metrology system and a method therefor are provided herein. In the system, a set of process data is gathered and clustered according to a plurality of predetermined patterns. The clustered set of process data is calculated according to the corresponding pattern, so as to obtain a comparison result. If the obtained result meets a desired output, a corresponding step is performed based on the result. In one case, the corresponding step is a normal sampling step if the clustered set of process data meets the corresponding pattern. If the clustered set of process data does not meet the corresponding pattern, an alarm is generated thereby, and the corresponding equipment may be shut down. In another case, the corresponding step is a maintenance, repair, and overhaul step if the clustered set of process data meets the corresponding pattern.

Abstract: A laser processing apparatus is provided wherein a laser beam of a wavelength which passes through a wafer having a surface on which a plurality of devices are disposed is irradiated along a schedule division line to separate the adjacent devices from each other to form a modification layer which continuously extends in a given length in the inside of the wafer. A mark portion is displayed in an overlapping relationship with a picked up image obtained by image pickup of a wafer on a display unit. If the mark portion is moved to a desired position of the picked up image displayed on the display unit, then coordinates which correspond to the desired position of the picked up image are stored as a start point or an end portion of a scheduled division line, along which the modification layer is to be formed, into a storage unit.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: Disclosed is an apparatus and method for yield enhancement of making a semiconductor device. The apparatus for yield enhancement of making a semiconductor device comprises: a semiconductor device comprising an epitaxial layer in which a defect is included, and a photo-resistor on the epitaxial layer and covering the defect; an image recognition system to detect and identify a location of the defect; and an exposing module comprising a first light source to expose a part of the photo-resistor substantially corresponding to the detected defect identified by the image recognition system.

Abstract: Disclosed is a method for yield enhancement of making a semiconductor device. The method for yield enhancement of making a semiconductor device comprises the steps of: providing the semiconductor device comprising an epitaxial layer including a defect; forming a dielectric layer on the epitaxial layer; detecting and identifying a location of the defect; and etching the dielectric layer and leaving a part of the dielectric layer to cover an area substantially corresponding to the detected defect. The semiconductor device made by the method is also disclosed.

Abstract: Inventive systems and methods for the generation of energy using thermophotovoltaic cells are described. Also described are systems and methods for selectively emitting electromagnetic radiation from an emitter for use in thermophotovoltaic energy generation systems. In at least some of the inventive energy generation systems and methods, a voltage applied to the thermophotovoltaic cell (e.g., to enhance the power produced by the cell) can be adjusted to enhance system performance. Certain embodiments of the systems and methods described herein can be used to generate energy relatively efficiently.

Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.

Abstract: A flat panel display device includes a pixel circuit provided on a substrate, a pixel wiring, an inspection pad connected to the pixel circuit through the pixel wiring, a main wiring separated from the inspection pad by a gap, and a common electrode covering substantially the entire substrate and electrically connecting the inspection pad to the main wiring.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Abstract: The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract: Methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis are provided. One method for measuring a characteristic of a substrate includes removing a portion of a feature on the substrate using an electron beam to expose a cross-sectional profile of a remaining portion of the feature. The feature may be a photoresist feature. The method also includes measuring a characteristic of the cross-sectional profile. A method for preparing a substrate for analysis includes removing a portion of a material on the substrate proximate to a defect using chemical etching in combination with an electron beam. The defect may be a subsurface defect or a partially subsurface defect. Another method for preparing a substrate for analysis includes removing a portion of a material on a substrate proximate to a defect using chemical etching in combination with an electron beam and a light beam.

Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

Abstract: A method for manufacturing a thin film photoelectric conversion module includes the steps of forming a plurality of photoelectric conversion elements connected in series on a substrate, and carrying out reverse bias processing simultaneously on a group of photoelectric conversion elements including a plurality of the photoelectric conversion elements positioned with one or a plurality of the photoelectric conversion elements interposed between each of them, by applying a plurality of voltages electrically isolated from one another to the group of photoelectric conversion elements.

Abstract: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films.

Abstract: A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.

Abstract: In one embodiment, a pattern inspection method is disclosed. The method can include predicting an edge shape at a given future time with respect to the same inspection target pattern, setting a threshold corresponding to a required specification of the inspection target pattern, and predicting the time when the inspection target pattern fails to meet the required specification from the predicted edge shape and the threshold. The method can further include taking a plurality of images concerning the inspection target pattern at different times by use of an imaging apparatus, detecting edges of the obtained images, respectively, matching the detected edges of different imaging times, and obtaining a difference between corresponding edges to generate a difference vector after the matching. The edge shape of the future time can be predicted based on the generated difference vector and an interval between the imaging times.

Abstract: A method is disclosed for localizing product yield variability to a process module. The method includes obtaining fail rate and critical area data for each process module layer in a number of test chips. A variance in a defect density (DD) probability density function (PDF) is determined based on the obtained fail rate and critical area data for each process module layer. A percent contribution from each process module layer to the variance in DD PDF is determined. Based on the determined percent contribution to the variance in DD PDF from each process module layer, one or more process module layers are identified as contributing to the determined variance in the DD PDF. Additionally, a method is provided to assess the impact on product yield due to reduction in the yield variability associated with a particular process module layer.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: A semiconductor device in one embodiment includes a wiring board having a wiring pattern; an N semiconductor elements(where N denotes a natural number equal to or greater than 2) mounted on a wiring board; and a current detection parts for detecting a current flowing through m semiconductor elements (where m denotes a natural number equal to or greater than 1 but less than M) of M semiconductor elements(where M denotes a natural number equal to or greater than 1 but equal to or less than N) mounted on the wiring board and selected from the N semiconductor elements. The M semiconductor elements are electrically connected in parallel through the wiring pattern, and the m semiconductor elements are electrically connected in parallel to the other semiconductor elements of the M semiconductor elements through the current detection part.

Abstract: A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: The present invention provides an apparatus and method for rapid and uniform thermal treatment of semiconductor workpieces in two closely arranged thermal treatment chambers with a retractable door between them. The retractable door moves in between two thermal treatment chambers during heating or cooling process, and additional heating and cooling sources are provided for double-side thermal treatment of the semiconductor workpiece.

Abstract: A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

Abstract: A method for manufacturing a thin film photoelectric conversion module comprising the steps of: (A) forming a plurality of divided strings by dividing a string, in which thin film photoelectric conversion elements provided by sequentially laminating a first electrode layer, a photoelectric conversion layer and a second electrode layer on the surface of an insulating substrate are electrically connected in series, into a plurality of strings by dividing grooves, electrically insulating and separating the first electrode layer and the second electrode layer one from the other and extending in a serial connection direction; and (B) performing reverse biasing by applying a reverse bias voltage to each of thin film photoelectric conversion elements of the divided string.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: A nitride-based semiconductor light emitting device having a structure capable of improving optical output performance, and methods of manufacturing the same are provided. The active layer may include a first barrier layer formed of InxGa(1-x)N (0.01?x?0.05) on a n-type semiconductor layer, a first diffusion barrier layer formed of InyGa(1-y)N (0?y<0.01) on the first barrier layer, and doped with an anti-defect agent including at least one of an N (nitrogen) element and a Si (silicon) element, a quantum well layer formed of InzGa(1-z)N (0.25?z?0.35) on the first diffusion barrier layer, a second diffusion barrier layer formed of InyGa(1-y)N (0?y<0.01) on the quantum well layer, and doped with an anti-defect agent including at least one of an N element and a Si element, and a second barrier layer formed of InxGa(1-x)N (0.01?x?0.05) on the second diffusion barrier layer.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.

Abstract: The present invention relates to a defect inspection apparatus for inspecting defects in patterns formed on a semiconductor device, on the GUI of which for the confirmation of the inspection results an area is provided for displaying any one of or facing each other the features amount of defects, and the image during inspection or the reacquired image, and on the GUI of which a means is provided for setting the classification class and importance of the defects, and based on the classification class and the importance of the defects information set by this setting means, the classification conditions or the defect judging conditions are automatically or manually set so that the inspection conditions may be set easily.

Abstract: The invention provides a method of repairing the pixel structure, and the method includes the following. First, an electrical connection between the current control unit and the power line is cut. The power line is then electrically connected to the redundant active device, so that the current control unit and the redundant active device control the current provided by the power line. The invention provides a method of repairing the organic electro-luminescence display unit, suitable for repairing the above-mentioned organic electro-luminescence display unit, and the method includes the following. First, an electrical connection between the current control unit and the power line is cut. The power line is electrically connected to the redundant active device, so that the current control unit and the redundant active device control the current passing through the organic electro-luminescence layer.

Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract: A semiconductor oxidation apparatus is provided with a sealable oxidation chamber defined by walls, a base provided within the oxidation chamber and configured to support a semiconductor sample, a supply part configured to supply water vapor into the oxidation chamber to oxidize a specific portion of the semiconductor sample, a monitoring window provided in one of the walls of the oxidation chamber and disposed at a position capable of confronting the semiconductor sample supported on the base, a monitoring part provided outside the oxidation chamber and capable of confronting the semiconductor sample supported on the base via the monitoring window, and an adjusting part configured to adjust a distance between the base and the monitoring part.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: An exemplary TFT array substrate includes: an insulating substrate (201), a gate line (23) and a repair structure (272) arranged on the insulating substrate, a gate insulating layer (204) covering the gate line and the repair structure; a data line (27) arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The repair structure has a gap (274). The gap of the repair structure is located at where the repair structure overlapping to the gate line.

Abstract: To manufacture a photovoltaic device through a first step of sequentially stacking a transparent electrode, a photovoltaic layer, and a rear surface electrode to thereby form a structure in which photovoltaic cells are serially connected, a second step of measuring characteristics of the photovoltaic cell; and a third step of removing, according to a result of measurement, the transparent electrode, the photovoltaic layer, and the rear surface electrode along the serial connection direction, to thereby divide the serially connected photovoltaic cells into a plurality of regions.

Abstract: A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a first compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the first compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing or separating off the structural defect by irradiating the first compartment element and a second compartment element with a laser beam so as to intersect a boundary section between the first compartment element including the portion in which the structural defect exists and the second compartment element adjacent to the first compartment element.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film.

Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.