Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.

Abstract: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A method for inspecting a pattern includes measuring, in a first direction, a width of a reference pattern at plural positions in the reference patter; measuring, in a second direction, a width of the reference pattern at the plural positions. Comparing the first and second width and determining which of the first and second widths is shortest; extracting a defect in a pattern to be inspected; and evaluating the extracted defect depending on the determined direction.

Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Abstract: By performing a contingency-based correlation test of measurement data, such as defect data, with respect to electrical test data after progressively filtering the measurement data, an enhanced analysis of process flow characteristics may be accomplished. Consequently, an efficient yield loss estimation may be performed.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may include clone test vehicle circuit patterns and/or clone test vehicle vias (1902). The presence of one or more defects (1904) in the one or more clone layers (1908) is an indicator of a tendency of the product circuit pattern to impact yield of a succeeding layer to be formed over the product circuit pattern in a product (1910).

Abstract: One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment.

Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Abstract: Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package.

Abstract: Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.

Abstract: An apparatus for monitoring gas flow in a semiconductor manufacturing equipment, includes an exhaust line, a flow amount measuring unit, and a controller unit having a first input electrically connected to the flow amount measuring unit and a second input having a predetermined reference value, the controller unit having the capability of comparing data in the first input to the predetermined reference value in the second input and generate a signal when the data in the first input exceed the predetermined reference value. The apparatus of the present invention may be incorporated into a gas delivery system employed in semiconductor manufacturing to detect gas leaks.

Abstract: Systems and methods for repairing defects on a specimen are provided. A method may include processing a specimen, detecting defects on the specimen, and repairing one or more of the defects. An additional method may include detecting defects on a specimen, repairing one or more of the defects, and inspecting the specimen to detect defects remaining on the specimen subsequent to repair. A system may include a process chamber, a measurement device configured to detect defects on a specimen, and a repair tool configured to repair one or more of the defects detected on the specimen. An additional system may include a measurement device, a repair tool, and an inspection tool configured to detect defects remaining on the specimen subsequent to repair. The systems may also include a processor configured to alter a parameter of an instrument coupled to the repair tool in response to output from the measurement device.

Abstract: It is an object of the present invention to provide a method of manufacturing a display device, which can display images favorably by insulating a short-circuit portion between an anode and a cathode. Further, it is another object of the invention to provide a method of manufacturing a display device, which can prevent intrusion of moisture so as to inhibit deterioration of a light emitting element when the short-circuit portion between the anode and the cathode is insulated. Specifically, the invention provide a method of manufacturing a display device, wherein a reverse bias voltage is applied to the light emitting element including an electro-luminescent material between the anode and the cathode so as to insulate the short-circuit portion between the anode and the cathode at a temperature of from ?40° C. to 8° C., more preferably, from ?25° C. to 8° C.

Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.

Abstract: The present invention is generally directed to various methods and systems for calibrating degradable components using process state data. In one illustrative embodiment, the method includes providing a tool comprised of at least one process chamber, providing at least one process state sensor that is adapted to obtain process state data regarding at least one characteristic of a process environment established in the chamber in performance of a process operation, operatively coupling at least one of a new or repaired degradable component to the tool, and calibrating the new or repaired degradable component based upon the process state data. In further embodiments, the method comprises processing a plurality of additional workpieces in the tool after the new or repaired degradable components have been calibrated using process state data in accordance with one aspect of the present invention.

Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.

Abstract: In a method of opening of a housing of a plastic-housed electronic module by a laser, the electronic module is protected from the effects of the laser beam and the laser beam is stopped at a suitable time by providing an end point signal detection due to the laser beam impinging on a protective layer. Thereby, after opening the housing, electrical measurements can be carried out on the electronic module.

Abstract: A method and system for identifying a defect or contamination on a surface of a sample. The system operates by detecting changes in work function across a surface via both vCPD and nvCPD. It utilizes a non-vibrating contact potential difference (nvCPD) sensor for imaging work function variations over an entire sample. The data is differential in that it represents changes in the work function (or geometry or surface voltage) across the surface of a sample. A vCPD probe is used to determine absolute CPD data for specific points on the surface of the sample. The combination of vibrating and non-vibrating CPD measurement modes allows the rapid imaging of whole-sample uniformity, and the ability to detect the absolute work function at one or more points.

Abstract: A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trenches along the conductive line, and at least one connecting portion disposed in each trench connecting the inner conductive portion and the outer conductive portions.

Abstract: A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contact potential difference data and processing that data to identify a pattern characteristic of the defect or contamination.

Abstract: Briefly, test wafer reuse techniques.

Abstract: A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contact potential difference data and processing that data to identify a pattern characteristic of the defect or contamination.

Abstract: The present invention generally relates to semiconductor processing, and in particular to methods and systems for analyzing photolithographic reticle defects that include detecting soft defects on a reticle and analyzing the material composition of the defects for a particular chemical signature. Specifically, the present invention scans and images a soft defect via an optical inspection scan of a reticle, mills the defect using a Focused Ion Beam, and analyzes the defect for signatures using Electron Spectroscopy for Chemical Analysis and/or Fourier Transform Infrared Spectroscopy. The present invention thus provides for real-time analysis of the chemical composition of a soft defect on a reticle without the need for a defect identification navigation system. According to an aspect of the present invention, reticle defects can be monitored without removal of a pellicle, thus facilitating increased throughput and decreased cost in reticle repair and/or cleaning.

Abstract: A sealing layer is provided on the surface of a substrate such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of the electronic devices to higher level circuit structures. The wafer is then divided or “singulated” to provide individual semiconductor dice having their active surfaces covered by the sealing layer. In this manner, the sealing layer initially acts as a stencil for forming the discrete conductive elements and subsequently forms a chip scale package structure to protect the semiconductor dice from the environment.

Abstract: A semiconductor manufacturing method whereby reactive gas processing such as selective epitaxial growth can be carried out with high precision by correctly adjusting conditions during processing is performed by a semiconductor manufacturing apparatus which can restrict increases in the moisture content, prevent heavy metal pollution and the like, and investigate the correlation between moisture content in the process chamber and outside regions. The moisture content in a reaction chamber and in a gas discharge system of the reaction chamber are measured when a substrate is provided, and the conditions for reactive gas processing are adjusted based on the moisture content.

Abstract: A wafer edge inspection method and apparatus include a review tool that captures images of the semiconductor wafer. According to various embodiments, the present invention also includes a map of points of interest proximate to the edge of the wafer, automatic image capturing at the points of interest, fake defect locations defining the points of interest, a database in which the images are stored and computer-searchable for detailed defect analysis, a software tool for controlling the method and apparatus and/or context information identifying the points of interest, the inspected wafer and/or the fabrication station/step preceding the inspection.

Abstract: A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contact potential difference data and processing that data to identify a pattern characteristic of the defect or contamination.

Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A semiconductor component having a monitoring structure suitable for monitoring metal migration of a metallization system and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A first extrusion monitoring element is formed over the major surface. A notched test element is formed over the first extrusion monitoring element. A second extrusion monitoring element is formed over the notched test element. A current is conducted through the notched test element. The resistance between the notched test element and at least one of the first and second extrusion monitoring elements is monitored to determine if a short has been created.

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract: One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next, the system measures properties of the layer using electromagnetic radiation. The properties of the layer measured are used to determine an index of refraction for the layer. The system then solves for the composition of the layer using the index of refraction.

Abstract: A method and system are provided for analyzing error signals based on fault detection. The method comprises detecting a fault associated with a processing of a workpiece in a manufacturing system having a plurality of processing tools, identifying at least one of the processing tools that processes the workpiece, and providing an error signal to the at least one of the identified processing tools to perform diagnostics based on the detected fault.

Abstract: A fabrication process for a tunneling magnetoresistance (TMR) sensor is disclosed. In particular, a unique method of forming a barrier layer of the TMR sensor is utilized so that the TMR sensor exhibits good magnetic and TMR properties. In one particular example, the barrier layer is formed by depositing a metallic film in an argon gas in a DC magnetron sputtering module, depositing an oxygen-doped metallic film in mixed xenon and oxygen gases in an ion-beam sputtering module, and oxidizing these films in an oxygen gas in an oxygen treatment module. This three-step barrier layer formation process minimizes oxygen penetration into ferromagnetic (FM) sense and pinned layers of the TMR sensor and optimally controls oxygen doping into the barrier layer. As a result, the FM sense and pinned layers exhibit controlled magnetic properties, the barrier layer provides a low junction resistance-area product, and the TMR sensor exhibits a high TMR coefficient.

Abstract: An array test is performed during the process of panel formation, such as at a stage where a driving TFT which supplies a drive current for an organic EL element is completed and an anode of the organic EL element has been formed on the TFT. Then, with regard to a defective pixel, a line connecting the driving TFT and the anode is disconnected using a laser. After the line has been thus disconnected, a planarization insulating film is formed, and this film fills the holes caused by the laser irradiation. It is thus possible to suppress deterioration of pixels and also effectively darken a defective pixel using laser.

Abstract: Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

Abstract: The present invention relates to a tool for analyzing by priority a defect having a high possibility of causing an electrical failure when inspecting a particle and a pattern defect in a piece of work which constitutes an electronic device such as a semiconductor integrated circuit, and relates to a system therefor. On the basis of the result of comparison between defect information which is the result of inspection by an inspection tool and layout data stored in an auxiliary storage device, or on the basis of the result of reinspection by comparison between a defect and a wiring pattern as a background by an inspection processing operation unit, an object to be reviewed is selected using review conditions stored in the auxiliary storage device.

Abstract: A sealing layer is provided on the surface of a substrate such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of the electronic devices to higher level circuit structures. The wafer is then divided or “singulated” to provide individual semiconductor dice having their active surfaces covered by the sealing layer. In this manner, the sealing layer initially acts as a stencil for forming the discrete conductive elements, and subsequently forms a chip scale package structure to protect the semiconductor dice from the environment.

Abstract: A method produces a semiconductor structure on a substrate. Then, a protective layer is applied to the semiconductor structure. To fabricate a further semiconductor structure that is to be formed on the substrate, intermediate processes, which lead to the formation of cracks in the protective layer, are carrier out. The protective layer is repaired with the aid of a repair layer.

Abstract: A method of fabricating an active matrix organic light emitting diode display is described. A substrate having an emitting region and a non-emitting region thereon is provided. Pixel structures are formed on the substrate in the emitting region, and a power line electrically connected with the pixel structures is formed on the substrate in the non-emitting region at the same time. Then, a cap is deposited above the substrate and bonded with the substrate. The cap covers the emitting region of the substrate and the power line. Since the power line is designed inside the cap, the cap can protect the power line from damage of the outside environment thus improving the lifetime of the display.

Abstract: A method of repairing organic light-emitting element pixels for repairing an organic light-emitting element having a substantial short circuit portion or portions. The method includes an electrical testing step and an insulator-forming step. The organic light-emitting element includes an anode substrate, an organic functional layer and a cathode. In this case, a current or voltage is applied to the anode substrate and the cathode of the organic light-emitting element respectively in the electrical testing step, so that the short circuit portion or portions of the organic light-emitting element are transformed to an open circuit portion or portions. In the insulator-forming step, an insulator is formed at the open circuit portion or portions of the organic light-emitting element. The invention also discloses a method of repairing organic light-emitting element pixels, which further includes an electrical detection step.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.