Abstract: An image sensor includes a semiconductor substrate; first pixels laid out above cavities provided within the semiconductor substrate, the first pixels converting thermal energy generated by incident light into an electric signal; supporting parts connected between the first pixels and the semiconductor substrate, the supporting parts supporting the first pixels above the cavities; and second pixels fixedly provided on the semiconductor substrate without via the cavities, wherein a plurality of the first pixels and a plurality of the second pixels are laid out two-dimensionally to form a pixel region, and each of the second pixels is adjacent to the first pixels.

Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.

Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices. Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.

Abstract: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: A nonvolatile storage device includes a plurality of bit lines 21 arranged in a column direction on a substrate; a plurality of word lines 35 arranged in a row direction on the substrate; a memory cell array 20 having a plurality of memory cells 31, where a store state of each of the memory cells 31 changes according to an electric signal relatively applied to the word line 35 and the bit line 21; a word line selection unit having a needle 51 relatively movable with respect to the substrate which comes into contact with one word line 35, setting the word line 35 in contact with the needle 51 to a selection state; and a sense amplifier 48 detecting through the bit line an electrical signal exhibiting the store state of the memory cell 31 to be connected to the word line.

Abstract: A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Abstract: A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an electrode having a minimized work function variation include methods of eliminating concentric circles of material having different work functions. Exemplary electrodes include electrode structures having concentric circles of materials with different work functions, wherein this difference in workfunction has been minimized by recessing these materials within an opening in a dielectric and forming a third conductor, having a uniform work function, over said recessed materials.

Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.

Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.

Abstract: A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is formed in the first insulation film in the wiring region, a first plug is formed by filling a conductive material in the first contact opening. A second insulation film is formed on the first insulation film. A second contact opening, in which the first plug is exposed, and a stopper opening, in which the first insulation film of the fuse region is exposed, are formed in the second insulation film. A second plug is formed by filling the second contact opening with a conductive material and a stopper film is formed by filling the stopper opening with conductive material.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further includes a second layer formed on the first layer, the second layer including a hole exposing a portion of the first layer, the exposed portion of the first layer having a lower conductivity. The method includes forming a first layer on a substrate, the first layer having a higher conductivity, forming a second layer on the first layer, exposing a portion of the first layer by forming a hole in the second layer, performing a process on at least the exposed portion of the first layer, the process decreasing the conductivity of the exposed portion. The exposed portion including the lower conductivity or higher resistivity may block heat from conducting in the first layer.

Abstract: An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

Abstract: The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed over the substrate, and the opening exposes the two adjacent second conductive type drain regions and the device isolation structure between the two adjacent second conductive type drain regions. A portion of the device isolation structure exposed by the opening is removed, and then a first conductive type well extension doped region is formed in the substrate exposed by the opening. A well pick-up conductive layer is formed in the opening. Dummy bit lines electrically connecting the well pick-up conductive layer are formed over the substrate.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method directs the first and second laser beams onto distinct first and second structures in the row. The second spot is offset from the first spot by some amount in a direction perpendicular to the lengthwise direction of the row. The method moves the first and second laser beam axes relative to the semiconductor substrate along the row substantially in unison in a direction substantially parallel to the lengthwise direction of the row.

Abstract: A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity type well section (22) and are arranged on the semiconductor substrate (10); a second conductivity type first conductive layer (21), which is a lower layer of the one or more elements (6), is in contact with the second conductivity type well section (22), and connects the second conductivity type well section (22) of the one or more elements (6) with the voltage supplying terminal (26); and a first conductivity type second conductive layer (11) formed in contact with a lower side of the first conductive layer (21).

Abstract: A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed over the substrate, and the opening exposes the two adjacent second conductive type drain regions and the device isolation structure between the two adjacent second conductive type drain regions. A portion of the device isolation structure exposed by the opening is removed, and then a first conductive type well extension doped region is formed in the substrate exposed by the opening. A well pick-up conductive layer is formed in the opening. Dummy bit lines electrically connecting the well pick-up conductive layer are formed over the substrate.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the first substrate and the second substrate while disposing at least a part of a functional element within a space between the first region and the second region; obtaining a plurality of first divisional substrates by cutting the first substrate at each of the first regions, after the connecting of the first substrate and the second substrate; forming a sealing film covering the plurality of the first divisional substrates on the second substrate, after cutting the first substrate; obtaining a plurality of second divisional substrates by cutting the second substrate at each of the second regions, after forming the sealing film; and obtaining a plurality of individual electronic devices.

Abstract: A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.

Abstract: Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.

Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.

Abstract: The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity

Abstract: A magnetic tunnel junction device with a compositionally modulated electrode and a method of fabricating a magnetic tunnel junction device with a compositionally modulated electrode are disclosed. An electrode in electrical communication with a data layer of the magnetic tunnel junction device includes a high resistivity region that has a higher resistivity than the electrode. As a result, a current flowing through the electrode generates joule heating in the high resistivity region and that joule heating increases a temperature of the data layer and reduces a coercivity of the data layer. Consequently, a magnitude of a switching field required to rotate an alterable orientation of magnetization of the data layer is reduced. The high resistivity region can be fabricated using a plasma oxidation, a plasma nitridation, a plasma carburization, or an alloying process.

Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

Abstract: A semiconductor manufacturing device includes a prober whose needles are at once engaged for contacting pads of two chip forming regions within a wafer. In one chip forming region, trimming is performed, while in the other chip forming region, inspecting posterior to trimming is performed.

Abstract: A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trenches along the conductive line, and at least one connecting portion disposed in each trench connecting the inner conductive portion and the outer conductive portions.

Abstract: A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.