Abstract: A method and system for an integrated singulation process for electrically testing semiconductor devices in a strip, singulating the semiconductor devices and inspecting the semiconductor devices. An electrical tester marks a code on the semiconductor devices indicating whether each semiconductor device passed an electrical test. An optical code reader reads the code and stores the test results in memory. A singulation machine singulates the semiconductor devices into individual semiconductor devices and a sorter discards the semiconductor devices which failed the electrical tests. An inspection machine inspects the dimensions of each semiconductor device and a sorter discards the semiconductor devices which failed the inspection. The inspection machine outputs the semiconductor devices which passed both the electrical test and inspection.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: Methods and apparatus for manufacturing a semi-custom integrated circuit by using a standard mask and a custom mask to select from a standardized set of features in a way that obviates the need to create a customized mask containing only the selected features, and mask sets created using such methods and apparatus. For some integrated circuit fabrication processes, the second mask has an additional purpose, so it is not created only to perform this selection function. For some fabrication processes, the selection can be achieved without use of additional processing steps.

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: A method of manufacturing integrated circuits having single and multiple device modes is described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a “by n” input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a “×n” configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a “×2n” configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features and a method of fabricating the same.

Abstract: The specification describes a CMOS compatible technique for programming MOS ROM devices. The technique involves doping the polysilicon gates of selected ROM devices with impurities having a type complementary to the channel, thereby raising the threshold voltage of those selected devices to a value above the operating voltage of the memory array. The programming step can be performed at the same time the CMOS gates are complementary doped thus allowing the ROM array to be programmed without additional processing steps.

Abstract: On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.

Abstract: An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in the opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming a recessed chalcogenide-metal ion material comprises forming a glass material to be recessed approximately 50% or less, in the opening in the dielectric material, forming a metal material on the glass material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Abstract: The semiconductor device comprises a blocking layer 12 formed on a substrate 10, an insulation film 14 formed on the blocking layer 12, and a fuse 22 formed on the insulation film 14. The blocking layer 12 is formed below the fuse 22, whereby the fuse is disconnected by laser ablation, and the laser ablation can be stopped by the blocking layer 12 with good controllability without damaging the substrate. The fuses to be disconnected can be arranged at a very small pitch, which can improve integration of the fuse circuit.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the first insulating film, a first, and a second impurity regions formed in the semiconductor substrate on both sides of the conductive layer patterns, a second insulating film formed on the first insulating film inclusive of the conductive layer patterns, a contact hole formed in the second insulating film on the conductive layer patterns, a plug formed in each of the contact holes, and wordlines formed the second insulating film inclusive of the plugs.

Abstract: A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device so as to dope portions of the sidewall spacers on one side of each of the digit lines while sidewall spacers opposed thereto and adjacent bit contacts are shielded from the dopant. Doped regions of the sidewall spacers may be removed with selectivity over undoped regions thereof to expose connect regions of each conductive element of each digit line. A conductive strap may then be formed to electrically link each connect region to its corresponding bit contact. Semiconductor devices including the conductive straps are also disclosed.

Abstract: The present invention comprises a single-substrate multiple chip module (MCM) assembly. The MCM assembly includes a repair-package-site ready MCM board having a top surface and a bottom surface, the top surface further includes a plurality of chip connection trace lines include a chip-select line. The MCM assembly further includes a plurality of bare integrated circuit (IC) chips mounted directly on the top surface of the MCM board each chip connected to the plurality of chip connection trace lines on the top surface. The repair-package-site ready MCM board further includes at least a repair-package-site disposed on the bottom surface having a plurality of connection terminals arranged according to a standard repair packaged-chip footprint. Each of the connection terminals is connected to a via connector disposed in the MCM board for electrically connecting to the conductive trace lines on the top surface.

Abstract: A semiconductor device e.g. a gate array, a mask ROM or the like produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device, wherein the upper-layer interconnections are connected exclusively with the selected ones of the foregoing units and are isolated from the unselected ones of the foregoing units, by a space or an insulator layer produced between the upper-layer interconnection and a layer in which conductive paths are produced for connecting the upper-layer interconnection and the foregoing units.

Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Abstract: A method of making a semiconductor device having fuses for repair, using a etch stop film to form an insulating film having a constant thickness. The etch stop film is patterned and then removed. Remaining portions of the insulating film have a constant thickness for each fuse box, thereby improving fabricating process yield and reliability.

Abstract: A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced. As a result, the word lines can be formed with minimum grid spacing and the risk of short-circuiting between adjacent word lines is eliminated by buried ploy stringers.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: Integrated circuit packages include an integrated circuit substrate having microelectronic devices therein and pads, wherein first ones of the pads are enabled to provide output data from the microelectronic devices, and wherein second ones of the pads are disabled to provide a reduced path width for the integrated circuit substrate. A packaging substrate includes terminals, a respective one of which is connected to a respective one of the pads, including the second ones of pads that are disabled to provide a reduced path width for the integrated circuit substrate. Accordingly, the same packaging substrates may be used with integrated circuit substrates having different path widths. In a preferred embodiment, the integrated circuit substrate includes a control circuit that disables the second ones of the pads to provide a reduced path width for the integrated circuit substrate.

Abstract: There is disclosed a memory cell having a reduced active area. The memory cell may be incorporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrudes above the semiconductor substrate. The memory element, such as a memory element formed of chalcogenide material, is disposed on the side of the protrusion to reduce the active area of the memory element as compared with conventional memory elements.

Abstract: Sewage water containing phosphate is passed through an anaerobic treatment chamber containing reductive-iron-dissolution (RID) material, such as ferric oxyhydroxide solids. The RID material releases ferrous ions into solution, which combine with the phosphate to produce ferrous-phosphate minerals, such as vivianite, which precipitate in the anaerobic chamber. Also, iron and phosphate remaining in the water can precipitate as ferric-phosphate minerals such as strengite, when the water is later aerated.

Abstract: A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such die may be employed in singulated fashion on a carrier substrate as an alternative to so-called “flip chip” die, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier, while other stacked vias are employed for individual access from each die level to the carrier through the back side of the lowermost die.

Abstract: A semiconductor nonvolatile storage that is an inter-gate insulating film breakdown type memory is configured by providing a field oxide film on a semiconductor substrate 1, a gate electrode on the field oxide film and a mask oxide film on the surface of the gate electrode, forming an opening m the mask oxide film and forming a memory oxide film on the gate electrode exposed thereat, providing a memory gate electrode of a size extending from over the memory oxide film to over the mask oxide film, and making the thickness of the memory oxide film thinner than the thickness of the mask oxide film.

Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.

Abstract: A library used for manufacturing a semiconductor IC and a method of manufacturing the semiconductor IC. The library includes structures designed with a predetermined design rule. The library has a main part including one or more circuit elements, and a connecting terminal connected to the main part. The connecting terminal has a width less than a minimum space between the conductive patterns of the predetermined design rule. The library further includes a head portion connected to the connecting terminal at an end thereof. A width of the head portion is greater than the minimum space between the conductive patterns of the predetermined design rule.

Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.

Abstract: A semiconductor device fabrication method is provided which comprises the steps of: (i) forming a plurality of high concentration diffusion layers of a second conductivity in a semiconductor substrate; (ii) forming a plurality of first gate electrodes extending perpendicularly to the high concentration diffusion layers of the second conductivity on the semiconductor substrate with a first gate insulating film interposed therebetween; (iii) implanting ions of a first conductivity into surface portions of the semiconductor substrate for device isolation by using the first gate electrodes as a mask; (iv) forming side wall spacers on side walls of the first gate electrodes; (v-i) implanting ions of the second conductivity into surface portions of the semiconductor substrate for formation of channel regions by using the first gate electrodes and the side wall spacers as a mask; (vi-i) forming a plurality of second gate electrodes on the ion-implanted channel regions between the first gate electrodes; and (vii) imp

Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Abstract: A CMOS semiconductor device is programmed by a laser beam which causes a PN junction in a silicon substrate to be permanently altered. This produces a leakage path between a program node and a tank region in the substrate; the program node can be an input to a transistor in a CMOS circuit, for example, so this node will always hold the transistor on or off depending whether or not it has been laser-programmed. Preferably, the tank region is of opposite type compared to the substrate, so the program node is electrically isolated from the substrate in either case.

Abstract: An apparatus and method for operatively substituting a replacement device for a defective component in an electrical assembly. The apparatus preferably includes a first primary site adapted to engage a first component, a second primary site adapted to engage a second component, and a replacement site adapted to engage a replacement device. The replacement site has a first dedicated replacement terminal coupled to a first dedicated terminal of the first primary site, and second dedicated replacement terminal coupled to a second dedicated terminal of the second primary site. The replacement site further includes a common replacement terminal coupled to common terminals of both the first and second primary sites. In operation, the replacement device is attached to the replacement site and coupled to the common replacement terminal. Additionally, the replacement device is coupled to the first dedicated replacement terminal if the replacement device is to substitute for the first component.

Abstract: A method of making a read only memory device includes forming a gate oxide layer and a silicon nitride layer in sequence above a silicon substrate. The gate oxide layer and the silicon nitride layer are etched to define a plurality of parallel strips extending in a first direction. Ions are implanted, using the parallel strips as masks, into the silicon substrate to form a plurality of buried bit lines extending in the first direction. A sidewall spacer is formed on respective sidewalls of the parallel strips. A silicide layer is formed over an exposed surface of the respective bit lines. An insulating layer is formed to cover any exposed surfaces, and fill a space located between adjacent parallel strips and above the bit lines. A portion of the insulating layer is removed to expose the silicon nitride layer and form a planar surface. The silicon nitride layer is patterned to form a plurality of coding areas. A polysilicon layer is formed to cover the coding areas as well as any other exposed surfaces.

Abstract: A method is provided for fabricating a ROM device for permanent storage of multi-level coded data therein. By the method, an array of MOSFET-based memory cells are first formed on a substrate, each being formed with an island-like gate region and a pair of source/drain regions. In accordance with customer specification, different groups of the memory cells are specified to respectively store a first, a second, a third, and a fourth value of the multi-level coded data. In the mask programming process, a first code-implantation process is performed to implant impurities into the respective channel regions of the second and fourth selected groups of the memory cells so as to vary the threshold voltage thereof. Then, an insulating layer is formed over the wafer, covering all of the memory cells. Next, a second code-implantation process is performed to form a plurality of contact windows in the insulating layer directly above the island-like gates of the first and second selected groups of the memory cells.

Abstract: A ROM structure and its method of manufacture using separate parallel trench bit lines for increasing memory component density as well as using a diode as the fundamental memory unit, each diode having a junction formed inside a bit line with a forward biased voltage of about 0.4 V and a reverse biased voltage dependent upon the doping condition in an N.sup.- region. At a junction between a word line and a bit line, either an ON state or an OFF state diode memory unit is created depending on whether a contact opening in the insulating layer for connection between the two is formed or not. When a definite operating voltage is applied to the word line, the stored information bit in the diode memory unit can be read off from the bit line by sensing a cut-off or a conducting current representing previous program coding of the diode memory unit.

Abstract: A matrix memory array includes a P-type semiconductor substrate, thick oxide columns separating active columns, gate rows, a gate insulator interposed at the locations where these rows cover the active columns, N-type islands limited by the thick oxide columns and the gate rows, first conductive columns at the pitch of the active columns, constituting bit lines, second conductive columns at a pitch which is twice that of the first columns, constituting reference lines, and connections between each island and a first or second conductive column.

Abstract: A method is provided for fabricating a read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented.

Abstract: A method for fabricating a semiconductor read-only memory (ROM) device of the type including a plurality of diode-type memory cells is provided. The ROM device is based on a silicon-on-insulation (SOI) structure in which all of the memory cells of the ROM device are formed in an insulating layer over a silicon substrate. The SOI structure allows for the prevention of leakage current between neighboring bit lines. The memory cells of the ROM device are each based on a P-N junction diode, which allows for a higher integration of the memory cells on a single chip than the use of MOSFET-based memory cells. The coding process is also easier to conduct.

Abstract: A cost-competitive, dense, CMOS compatible ZPROM memory array design and method of manufacture is disclosed. The method of manufacture includes a novel method for forming extremely thin diodes and thin strips of other materials such as conductors by using oxide spacers as an etching mask.

Abstract: After an insulating film is deposited over metal patterns, a resist film is coated over the whole surface of the insulating film until the surface of the resist film becomes flat. The resist film is removed by reactive ion etching until a partial surface area of the insulating film deposited over the metal patterns is exposed. Another photoresist film is coated on the surface to cover a part of the exposed areas of the insulating film and the resist film, exposed and developed to form a resist mask. The area not covered with the resist mask and the resist film is selectively removed by anisotropic etching. The resist mask and the resist film are removed to obtain a window having a width equal to the width of a convex of the insulating film. A method of manufacturing a semiconductor device that is capable of exposing a metal wiring layer at a high precision is provided.

Abstract: A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data therein. In the semiconductor structure of the ROM device, a plurality of insulator-filled trenches are formed for isolation of the diode-based memory cells. This feature allows the prevention of the punch-through effect when the ROM device is downsized. Further, the bit lines for the ROM device are formed with an increased junction depth such that the resistance of the bit lines can be reduced to allow an increase in the magnitude of the currents in the bit lines for easier detection and distinguishing of the binary state the currents represent.

Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time to the memory cells. The binary data stored in each memory cell is dependent on whether a contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value. The threshold voltage of the permanently-ON memory cells is about in the range from 0.4 V to 0.7 V.

Abstract: A method for securing confidential circuitry from observation by unauthorized inspection, and a secure circuit immune from unauthorized inspection according to the method. In one embodiment, confidential data or circuitry is placed on a face of separate silicon layers, each silicon layer having part of a circuit. Neither silicon layer is intelligible without the other, yet neither can be observed without destroying the other. The two silicon layers are juxtaposed, the face of the first silicon layer flush against and fused to the face of the second silicon layer, the confidential circuits on each silicon layer connecting directly with circuits on the other silicon layer without external connectors. Data stored on each face is erased or destroyed when the silicon layers are separated or one of the silicon layers is destroyed.

Abstract: A method for manufacturing an static random access memory (SRAM) cell (10) begins by manufacturing a fuse region (36) over a substrate (10). An etch stop layer (44) is formed overlying the fuse region (36) from resistor polysilicon material. In order for the fuse region (36) to be accessed and properly disabled, an opening (60) must be provided which stops on the etch stop layer (44). The etch stop (44) ensures a consistent and repeatable optimal thickness X of dielectric material above the fuse region (36) to provide for proper laser access and repair. The etch stop layer (44) therefore reduces wafer to wafer and die to die variation in thickness X and provides for a higher yield laser repair for each SRAM integrated circuit and every wafer processed using this methodology.

Abstract: A process for fabricating multi-stage memory cell units o semiconductor ROM device is disclosed. Each of the ROM device multi-stage memory cell units holds data bits that can be interpreted into any one of a number of voltage or current levels of more than two. The process is consisted of the steps of first forming a MOS transistor in the device substrate, and the transistor comprises a pair of source/drain regions and a gate structure. An insulating layer is then formed covering the transistor. A contact opening is then formed in each of the pair of source/drain regions. A resistor connecting across the source/drain regions of the transistor is then formed, and the resistor has each of its ends extending into corresponding one of the contact openings. Then, the memory cell unit is programmed at a first stage by optionally cutting or not cutting the resistor into electrically disconnected halves.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: A method of manufacturing a semiconductor device including the steps of: forming an insulating film on an electrical connection area; forming a contact hole in the insulating film; forming a crystalline semiconductor region in the contact hole; forming a wiring layer covering the contact hole; and selectively implanting ions over the wiring layer by using a resist mask to make the crystalline semiconductor region have a high resistance. A semiconductor device having customized wiring connections can be manufactured in a short term.

Abstract: The present invention is related to a flexible IC layout method utilized for an IC having a plurality of logic gates in a first direction connected with a plurality of logic gates in a second direction wherein each of the logic gates has at least one polysilicon region and each of the logic gates in the first direction has an output serving as an input of a corresponding one of the logic gates in the second direction, which includes a step of forming input terminals for the logic gates by ion implantation. The present invention is flexible because the addition or deduction of the number of the input terminals according to the present invention can be achieved by ion implantation.

Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.

Abstract: A method of forming bipolar ROM device on a semiconductor substrate comprises forming a collector region by doping with a dopant of a first polarity, forming an array of common base regions by doping with a dopant of an opposite polarity, forming a plurality of emitter regions selectively in the base regions by doping with a dopant of first polarity and diffusing the dopant into the emitter regions from doped conductors, which conductors are formed as an array of conductors disposed orthogonally relative to the array of common base elements. The conductors are connected to emitter regions traversed thereby and are isolated from other regions by dielectric layers selectively formed over the other regions to prevent diffusion of dopant therethrough to prevent formation of such emitter regions.

Abstract: In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region.