Abstract: A NOR type masked ROM device including a multiplicity of FETs each having a channel region, an insulated gate structure formed on the channel region, and a pair of current electrode regions disposed on the both sides of the insulated gate structure, wherein trenches are selectively formed in those FETs which are programmed to be turned off, between the insulated gate structure and at least one of the associated current electrode regions, and regions of opposite conductivity type to that of the current electrode regions are formed under the trenches.

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a gate oxide layer, a first polysilicon layer, and a first silicide layer are formed subsequently on the surface of a silicon substrate. The layers are patterned to form parallel strip-shaped configurations extending along a first direction on the surface of the silicon substrate. Next, impurities are implanted into the surface of the substrate in the areas between the strip-shaped configurations thereby constituting buried bit lines of the memory cells. Sidewall spacers are then formed on the sidewalls of the strip-shaped configurations. A second silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process, thereby improving the electrical conductivity of the buried bit lines. After that, the portions of the second silicide layer and the first polysilicon layer covering the coding region of the memory cells are removed.