Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: The present invention relates to a semiconductor memory device including a fuse box wherein the layout of a fuse box used to control a memory cell array is improved, a fuse box is divided into a plurality of blocks, and an index mark is applied to every fuse box or to every block so that a user may recognize each fuse box. In an embodiment, there is provided a semiconductor memory device including a fuse box comprising a plurality of cell matrices and a fuse box. The plurality of cell matrices are arranged adjacently each other. The fuse box is defined by a fuse barrier layer formed at a side of the plurality of cell matrices, wherein the fuse box comprises a plurality of cell matrices, wherein the fuse box comprises a plurality of fuses shared by the plurality of cell matrices, and the fuse barrier layer is configured to have a length long enough to be shared by the plurality of cell matrices.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: A method of controlling implantation dosages during coding of read-only memory (ROM) devices is disclosed. According to the method, a semi-manufactured ROM device having a plurality of gates with identically designed gate widths is formed, followed by the formation of a first photoresist layer over the semi-manufactured ROM device. The first photoresist layer is selectively exposed to develop a pattern of pre-code openings, with each pre-code opening being positioned over a word line and between two adjacent bit lines intersecting the word line and with the pre-code openings having substantially identical sizes. A second photoresist layer is then formed over the first photoresist layer, followed by selectively exposing the second photoresist layer to develop a pattern of real-code openings therein, with the real-code openings having substantially identical sizes. A tuned dosage of ions is then implanted through intersections of the real-code and pre-code openings to thereby code the ROM device.

Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.

Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.

Abstract: Irrespective of a specification of the controller, a plurality of TFTs are formed for the controller on a substrate in advance. Then, in accordance with a design of the controller, connection is achieved among sources, drains, and gates, which serve as three terminals in each of the plural TFTs, appropriately through a wiring formed on a layer different from the one where the plural TFTs are formed, so that the controller with a desired specification is formed. At this time, it is not required to use all the TFTs arranged on the substrate and some TFTs may remain unused depending on the specification of the controller.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

Abstract: A set (50) of one or more laser pulses (52) is employed to remove passivation layer (44) over a conductive link (22). The link (22) can subsequently be removed by a different process such as chemical etching. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.05 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly material removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each target area (51). Conventional wavelengths in the IR range or their harmonics in the green or UV range can be employed.

Abstract: A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple matrix structure in which each memory cell is formed at a cross-point of an upper and a lower linear electrode is employed, and an insulating material is selectively ejected to surfaces of electrodes at predetermined memory cell positions by using an inkjet head, the surfaces of the electrode at the predetermined memory cell positions are covered with the insulating material. A state is stored in accordance with the presence or the absence of the covering insulating film on the surface of the electrode at each memory cell position.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only, causing a conductive pathway to grow from cathode to anode. The amount of conductive pathway growth, and therefore the programming, depends, in part, on the availability of metal ions. It is important that the metal ions come only from the solid solution of the memory cell body. If additional metal ions are supplied from other sources, such as the sidewall edge at the anode interface, the amount of metal ions may not be directly related to the strength of the electric field, and the programming will not respond consistently from cell to cell. The embodiments described herein provide new and novel structures that block interface diffusion paths for metal ions, leaving diffusion from the bulk glass electrolyte as the only supply of metal ions for conductive pathway formation.

Abstract: An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in said opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming the recessed chalcogenide-metal ion material comprises forming a metal material being recessed approximately 10-90%, in the opening in the dielectric material, forming a glass material on the metal material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A method of fabricating a semiconductor device characterized in that the method includes the steps of forming basic structures of unit FETs on each of ‘m’ active layer regions more than the number of designed unit FETs and determining the number ‘n’ of desired basic structures on the basis of a drain current value of the semiconductor device predicted from a measured value of the drain current characteristics of one of the basic structures. The contact holes for electrical connections to electrodes of each of the unit FETs are formed for only the regions on ‘n’ basic structures in an inter-layer insulating film. In this manner, there is provided a method of fabricating a semiconductor device, the method being capable of improving degraded characteristics after the characteristics of TEG-FET have been measured.

Abstract: A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

Abstract: In one implementation, a non-volatile resistance variable device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on the body. The body includes a surface extending from one of the electrodes to the other of the electrodes. The surface has at least one surface striation extending from proximate the one electrode to proximate the other electrode at least when the body of said material is in a highest of selected resistance setable states. In one implementation, a method includes structurally changing a non-volatile device having a body formed of a voltage or current controlled resistance setable material and at least two spaced electrodes on the body. The body has a surface extending from one of the electrodes to the other of the electrodes, and the surface is formed to comprise at least one surface striation extending from proximate the one electrode to proximate the other electrode.

Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

Abstract: A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer, a stopping layer and a second dielectric layer. A gate oxide layer covers a portion of the upper surface of the substrate. A word line runs across the buried bit line to form a plurality of coding cells. The memory cells having a stack layer thereon are at a logic state “0” while the memory cells having a gate oxide layer thereon are at a logic state “1”.

Abstract: An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate plane. The stack intermediate planes of a stack have identical layouts, while chip select circuits which can be set irreversibly via contact areas are disposed on the chips, which chip select circuits enable an irreversible assignment of the contact areas to the stack intermediate planes.

Abstract: The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and the bottom surface. An integrated circuit is fabricated on the semiconductor wafer and includes a working set of discrete functional modules arranged into a central rectangular array of rows and columns defined by a boundary that includes four rectilinear sides and four corners. The integrated circuit further includes a spare set of discrete functional modules formed outside the boundary of the working set into at least one line that is disposed along a side of the rectangular array of the working set. If a discrete functional module in the working set is found to be defective, it can be replaced by a discrete functional module in the spare set.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Source and drain regions are disposed between gate electrodes of adjacent memory cells. Source regions are provided with polysilicon layers, in the form of a strip, as common source lines. Drain regions are connected as bit lines through polysilicon fillings to metallic interconnects applied to the top face of the semiconductor body.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element.

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.

Abstract: A method for making a small pore. The defined pore is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.

Abstract: A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.

Abstract: A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from one side of the fuse window, and another fuse wiring extended up to the bottom of the fuse body form the another side of the fuse window. Contact plugs are disposed on terminal portions of the fuse wirings respectively, the terminal portions facing to each other having a predetermined gap between them. The bottom surfaces of both terminal portions of the fuse body are electrically connected with the facing terminal portions of the fuse wirings through the contact plugs, respectively. The length of the fuse body is set so as to have a length not shorter than the predetermined gap and not exceeding a diameter of laser beam to blow off the fuse body.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A cascaded diode acting as all ESD protection device with reduced substrate leakage current is disclosed. The cascaded diode is composed of a chain of coupled similar elemental diodes, each composed of an n-well in a p-substrate, the n-well having p regions and n regions, and a deep n-well disposed under and connected to the n-well. The first elemental diode has its p region electrically connected to a pin or pad that is the higher potential end of a portion of an integrated circuit to be protected, its n region electrically connected to the p region of an intermediate elemental diode. The p region of an intermediate diode is connected electrically to the n region of the preceding elemental diode and the n region of an intermediate elemental diode is connected electrically to the p region of the following elemental diode.

Abstract: A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Abstract: The invention relates to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents volatilization of the chalcogenide memory material.

Abstract: A method for installing protective components in integrated circuits constructed from standard cells includes reserving sufficient space in the standard cells for at least one protective component, wiring the standard cells and determining which standard cells require a protective component and inserting at least one protective component into the standard cells. A place marker can mark the space required for a protective component in the integrated circuit layout. The protective component can be a protective diode. Protective component connections can be provided in the standard cells. The standard cells can be gate arrays.

Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process used for forming the metal vias. The metal lines are subsequently removed by either a mechanical method such as dicing with a diamond saw or by a chemical method such as wet etching. The method allows the fabrications of a wafer level package that has a multiplicity of elastomeric blocks formed on top as stress buffering layer without the CTE mismatch problem with other layers on the wafer.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.