Including Source Or Drain Electrode Formation Prior To Semiconductor Layer Formation (i.e., Staggered Electrodes) Patents (Class 438/161)
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Patent number: 11990512Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: GrantFiled: February 14, 2022Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Miao-Syuan Fan, Pei-Wei Lee, Ching-Hua Lee, Jung-Wei Lee
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Patent number: 11906826Abstract: Disclosed is a liquid crystal display device which can be used in a variety of situations and applications. The liquid crystal display device comprises: a first substrate comprising a first display region, a second display region, and a third display region wherein the first display region, the second display region, and the third display region are continuously formed; a second substrate having a form which fits the first substrate; and a liquid crystal interposed between the first substrate and the second substrate. The second display region is interposed between the first display region and the second display region. The second display region is curved, and the first display region and the second display region are substantially flat.Type: GrantFiled: January 5, 2023Date of Patent: February 20, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tetsuji Ishitani
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Patent number: 11435626Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.Type: GrantFiled: April 9, 2019Date of Patent: September 6, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hajime Kimura
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Patent number: 11393892Abstract: A display includes a plurality of first wirings which are provided on a first layer and each of which is arranged parallel to a first direction in a first area, and which are arranged on a second layer in a second area; a second wiring which is provided in the first layer in the first area and which is provided on a layer in the second area; and a third wiring which is provided on the first layer and arranged between the first wirings in the first area and which is arranged to intersect with first wirings in the second area. The first wirings is arranged to be inclined to the same side in the first direction in the second area. The second wiring is arranged to intersect with a portion of the plurality of first wirings in a plan view, in the second area.Type: GrantFiled: May 21, 2020Date of Patent: July 19, 2022Assignee: JAPAN DISPLAY INC.Inventors: Masumi Nishimura, Hiroshi Tabatake, Akihito Sato
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Patent number: 11251268Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: GrantFiled: July 23, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Miao-Syuan Fan, Pei-Wei Lee, Ching-Hua Lee, Jung-Wei Lee
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Patent number: 11114563Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.Type: GrantFiled: April 2, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
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Patent number: 9923056Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.Type: GrantFiled: December 2, 2016Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang
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Patent number: 9685471Abstract: The present invention provides a manufacture method of a thin film transistor substrate. In the same photolithographic process, the via deposing process is implemented to the gate isolation layer and the etching stopper layer is patterned. That is, the photolithographic process is not implemented but the oxide semiconducting pattern is formed directly after the gate isolation layer is formed. After the etching stopper layer is formed, the gate isolation layer and the etching stopper layer are patterned in the same photolithographic process. Comparing with the manufacture method of prior art, one photolithographic process can be eliminated. Meanwhile, the aperture ratio is raised by forming an open at the transparent conducting layer.Type: GrantFiled: July 2, 2014Date of Patent: June 20, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventors: Wenhui Li, Chihyuan Tseng
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Patent number: 9647127Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an insulating layer and a metal oxide semiconductor layer which are adjacent to each other, and the insulating layer is formed by steps of: forming a first silicon oxide film; and stabilizing the first silicon oxide film by filling a silicon dangling bond therein with a filling atom capable of being bonded to the silicon dangling bond.Type: GrantFiled: July 15, 2014Date of Patent: May 9, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xiang Liu, Woobong Lee
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Patent number: 9601597Abstract: A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.Type: GrantFiled: February 21, 2013Date of Patent: March 21, 2017Assignee: Pragmatic Printing LimitedInventors: Antony Colin Fryer, Richard David Price
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Patent number: 9525147Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.Type: GrantFiled: February 6, 2015Date of Patent: December 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qing Cao, Kangguo Cheng, Shu-Jen Han, Zhengwen Li, Fei Liu
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Patent number: 9349593Abstract: To improve electric characteristics of a semiconductor device including an oxide semiconductor. Alternatively, to improve reliability of a semiconductor device including an oxide semiconductor. In a transistor including a first oxide film, an oxide semiconductor film, a pair of electrodes in contact with the oxide semiconductor film, and a second oxide film in contact with the oxide semiconductor film and the pair of electrodes, oxygen is added to the first oxide film and the second oxide film in contact with the oxide semiconductor film and the pair of electrodes, so that oxygen vacancies are reduced. The oxygen is diffused to the oxide semiconductor film by heat treatment or the like; thus, oxygen vacancies in the oxide semiconductor film are reduced.Type: GrantFiled: December 2, 2013Date of Patent: May 24, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9337079Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.Type: GrantFiled: October 9, 2012Date of Patent: May 10, 2016Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Nicolas Loubet, Qing Liu, Shom Ponoth
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Patent number: 9219238Abstract: Disclosed is an organic thin film transistor array substrate and a method for manufacturing. The method increases the manufacturing efficiency of the organic thin film transistor array substrate. In the method, a pixel electrode, a source electrode, a data line and a drain electrode are formed on a substrate through one patterning process, where both of the pattern layer for the source electrode and the pattern layer for the data line and the drain electrode are located above the pixel electrode. An organic semiconductor layer and a gate insulating layer that covers the organic semiconductor layer are formed through one patterning process, where the organic semiconductor layer covers both of the pattern layer for the source electrode and the pattern layer for the data line and the drain electrode. A gate electrode and a gate line are formed through one patterning process on the substrate formed with the gate insulating layer.Type: GrantFiled: December 14, 2012Date of Patent: December 22, 2015Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Xuehui Zhang
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Patent number: 9214566Abstract: A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts. In the semiconductor device, the first oxide semiconductor film, the second oxide semiconductor film, and the oxide film are each formed using a IGZO film, where the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film, the first oxide semiconductor film has a higher indium content than the oxide film, the oxide film has a higher gallium content than the first oxide semiconductor film, and the first oxide semiconductor film has a higher gallium content than the second oxide semiconductor film.Type: GrantFiled: January 12, 2015Date of Patent: December 15, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9184134Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a dielectric layer on the semiconductor substrate. The semiconductor device structure also includes at least one conductive structure embedded in the dielectric layer. A plurality of crystal grains are composed of the conductive structure, and a ratio of an average grain size of the crystal grains to a width of the conductive structure ranges from about 0.75 to about 40.Type: GrantFiled: January 23, 2014Date of Patent: November 10, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Feng Lin, Chih-Chien Chi, Ching-Hua Hsieh
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Patent number: 9153664Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.Type: GrantFiled: May 23, 2014Date of Patent: October 6, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiyotaka Imai, Young-Gwon Kim, Shigenobu Maeda, Soon-Chul Hwang
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Patent number: 9136353Abstract: A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s).Type: GrantFiled: December 13, 2012Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hee Choi, Andrei Zoulkarneev
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Patent number: 9116383Abstract: A manufacturing method of a light barrier glass sheet, comprising: farming a metal layer (2) on a glass substrate (1); coating a first photoresist layer (3) on the metal layer (2), performing first exposure on the first photoresist layer (3) through a half tone mask, then performing first development on the first photoresist layer (3); removing partial region of the metal layer (2) through a first etching process; removing a partial thickness and a partial region of the first photoresist layer (3) through an ashing process; forming an insulating layer (4) on the exposed glass substrate (1), the exposed metal layer (2), the first photoresist layer (3) after the ashing process, and sidewalls of the photoresist layer (3) after the ashing process; removing the first photoresist layer (3), the insulating layer (4) on the first photoresist layer (3), and the insulating layer (4) on the sidewalls of the first photoresist layer (3) by a photoresist lifting-off process so as to form a via hole (7); forming a transpareType: GrantFiled: June 17, 2013Date of Patent: August 25, 2015Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Zheng Liu, Seung Min Lee, Seung Moo Rim, Huibin Guo
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Patent number: 9035305Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.Type: GrantFiled: September 25, 2014Date of Patent: May 19, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
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Patent number: 9012275Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.Type: GrantFiled: December 2, 2013Date of Patent: April 21, 2015Assignee: AU Optronics Corp.Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
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Patent number: 8975124Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.Type: GrantFiled: May 15, 2012Date of Patent: March 10, 2015Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
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Patent number: 8969884Abstract: A thin film transistor element is formed in each of a first aperture and a second aperture defined by partition walls, which further define a third aperture that is adjacent to the first aperture with a gap therebetween and is located in a direction, from the first aperture, differing from a direction of the second aperture. In plan view, at a bottom portion of the first aperture, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction differing from a direction of the third aperture, and at a bottom portion of one of the first and second apertures, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction differing from a direction of the other one of the first and second apertures.Type: GrantFiled: August 16, 2013Date of Patent: March 3, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 8946005Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.Type: GrantFiled: February 18, 2011Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventors: Je-Hun Lee, Do-Hyun Kim, Eun-Guk Lee, Chang-Oh Jeong
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Patent number: 8946730Abstract: In a thin film transistor device, partition walls define first, second, and third apertures. In plan view, at a bottom portion of the first aperture, a center of a total of areas of a source electrode portion and a drain electrode portion is offset from a center of area of the bottom portion in a direction differing from a direction of the third aperture, and at a bottom portion of one of the first and second apertures, a center a total of areas of a source electrode portion and a drain electrode portion is offset from a center of area of the bottom portion in a direction differing from a direction of the other one of the first and second apertures.Type: GrantFiled: August 16, 2013Date of Patent: February 3, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 8941115Abstract: A thin film transistor element includes a gate electrode, an insulating layer formed on the gate electrode, and partition walls formed on the insulating layer and defining a first aperture above the gate electrode. The thin film transistor element further includes, at a bottom portion of the first aperture, a source electrode and a drain electrode that are in alignment with each other with a gap therebetween, a liquid-philic layer, and a semiconductor layer that covers the source electrode, the drain electrode, and the liquid-philic layer as well as gaps therebetween. The liquid-philic layer has higher liquid philicity than the insulating layer, and in plan view of the bottom portion of the first aperture, a center of area of the liquid-philic layer is offset from a center of area of the bottom portion of the first aperture.Type: GrantFiled: August 16, 2013Date of Patent: January 27, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 8907344Abstract: A thin film transistor element is formed in each of adjacent first and second apertures defined by partition walls. In plan view of a bottom portion of the first aperture, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction opposite a direction of the second aperture, and in plan view of a bottom portion of the second aperture, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction opposite a direction of the first aperture.Type: GrantFiled: August 16, 2013Date of Patent: December 9, 2014Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 8901658Abstract: A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.Type: GrantFiled: December 4, 2012Date of Patent: December 2, 2014Assignee: E Ink Holdings Inc.Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Ted-Hong Shinn
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Patent number: 8895377Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.Type: GrantFiled: February 20, 2014Date of Patent: November 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8896065Abstract: A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region.Type: GrantFiled: April 14, 2008Date of Patent: November 25, 2014Assignee: Sharp Laboratories of America, Inc.Inventors: Hidayat Kisdarjono, Apostolos T. Voutsas
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Patent number: 8853017Abstract: An organic thin film transistor is disclosed, including a substrate formed of an organic insulating layer, a first layer deposited on the substrate using a plating technique to be used for forming a source electrode and a drain electrode, a second layer of a metal material deposited covering the first layer using a further plating technique to be used for forming the source electrode and the drain electrode with the metal material capable of forming an ohmic contact with an organic semiconductor material lower than the first layer, and an organic semiconductor layer over a region between the source electrode and the drain electrode, which are each formed with the first layer and the second layer. Also disclosed is an electric device provided with the organic thin film transistor.Type: GrantFiled: July 28, 2009Date of Patent: October 7, 2014Assignee: Sony CorporationInventors: Kazumasa Nomoto, Nobuhide Yoneya, Takahiro Ohe
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Patent number: 8846514Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.Type: GrantFiled: July 27, 2012Date of Patent: September 30, 2014Assignee: Samsung Display Co., Ltd.Inventors: Sang Ho Park, Yoon Ho Khang, Se Hwan Yu, Yong Su Lee, Chong Sup Chang, Myoung Geun Cha, Hyun Jae Na
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Patent number: 8823105Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.Type: GrantFiled: June 5, 2012Date of Patent: September 2, 2014Assignee: Sony CorporationInventor: Mao Katsuhara
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Patent number: 8816352Abstract: Disclosed herein is a display device including: a thin film transistor; and a wiring layer; wherein the thin film transistor includes a semiconductor layer, a gate electrode disposed so as to be opposed to the semiconductor layer, the gate electrode being different in thickness from the wiring layer, and a gate insulating film between the semiconductor layer and the gate electrode.Type: GrantFiled: February 3, 2012Date of Patent: August 26, 2014Assignee: Sony CorporationInventors: Yasuhiro Terai, Toshiaki Arai
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Patent number: 8802491Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.Type: GrantFiled: June 11, 2013Date of Patent: August 12, 2014Assignee: Sony CorporationInventor: Mao Katsuhara
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Patent number: 8796682Abstract: To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.Type: GrantFiled: November 1, 2012Date of Patent: August 5, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Motomu Kurata, Hideaki Kuwabara, Mari Terashima
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Patent number: 8796786Abstract: Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.Type: GrantFiled: April 5, 2013Date of Patent: August 5, 2014Assignee: Micron Technology, Inc.Inventor: Richard T. Housley
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Semiconductor device including first and second or drain electrodes and manufacturing method thereof
Patent number: 8785990Abstract: An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate, a gate insulating film over the gate electrode, a first source or drain electrode over the gate insulating film, an island-shaped semiconductor film over the first source or drain electrode, and a second source or drain electrode over the island-shaped semiconductor film and the first source or drain electrode. Further, the second source or drain electrode is in contact with the first source or drain electrode, and the island-shaped semiconductor film is sandwiched between the first source or drain electrode and the second source or drain electrode. Moreover, the present invention relates to a manufacturing method of the semiconductor device.Type: GrantFiled: January 4, 2012Date of Patent: July 22, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Honda -
Patent number: 8785264Abstract: According to an embodiment of the disclosed technology, a manufacture method of an organic thin film transistor array substrate is provided. The method comprises: forming a first pixel electrode, a source electrode, a drain electrode and a data line in a first patterning process; forming an organic semiconductor island and a gate insulating island in a second patterning process; forming a data pad region in a third patterning process; and forming a second pixel electrode, a gate electrode and a gate line in a fourth patterning process.Type: GrantFiled: May 23, 2012Date of Patent: July 22, 2014Assignee: BOE Technology Group Co., Ltd.Inventor: Xuehui Zhang
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Patent number: 8748224Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.Type: GrantFiled: August 4, 2011Date of Patent: June 10, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Toshinari Sasaki
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Patent number: 8748242Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.Type: GrantFiled: July 26, 2012Date of Patent: June 10, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8728882Abstract: A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.Type: GrantFiled: August 8, 2012Date of Patent: May 20, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jae Seung Hwang, Jae-Won Lee, Jun Seo
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Patent number: 8673708Abstract: A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.Type: GrantFiled: September 12, 2012Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
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Patent number: 8669146Abstract: A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.Type: GrantFiled: January 13, 2011Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 8669148Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.Type: GrantFiled: August 13, 2013Date of Patent: March 11, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8629010Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.Type: GrantFiled: October 21, 2011Date of Patent: January 14, 2014Assignees: International Business Machines Corporation, Karlsruher Institut Fuer Technologie (KIT)Inventors: Phaedon Avouris, Yu-Ming Lin, Mathias B. Steiner, Michael W. Engel, Ralph Krupke
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Patent number: 8623715Abstract: A method for fabricating a thin-film semiconductor device for display according to the present disclosure includes: preparing a glass substrate; forming, above the glass substrate, an undercoat layer including a nitride film; forming a molybdenum metal layer above the undercoat layer; forming a gate electrode from the metal layer by an etching process; forming a gate insulating film above the gate electrode; forming a non-crystalline silicon layer as a non-crystalline semiconductor layer above the gate insulating film; forming a polycrystalline semiconductor layer which is a polysilicon layer by annealing the non-crystalline silicon layer at a temperature in a range from 700° C. to 1400° C.; forming a source electrode and a drain electrode above the polysilicon layer; and performing hydrogen plasma treatment at a stage after the metal layer is formed and before the polysilicon layer is formed, using a radio frequency power in a range from 0.098 W/cm2 to 0.262 W/cm2.Type: GrantFiled: November 16, 2012Date of Patent: January 7, 2014Assignee: Panasonic CorporationInventors: Kenichirou Nishida, Hisao Nagai
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Patent number: 8598584Abstract: In the thin-film transistor device: the stacked thickness of either a source electrode or a drain electrode and a corresponding one of silicon layers is the same value or a value close to the same value as the stacked thickness of a first channel layer and a second channel layer; the stacked thickness of the first channel layer and the second channel layer is the same in a region between the source electrode and the drain electrode and above the source electrode and the drain electrode; the first channel layer and the second channel layer are sunken in the region between the source electrode and the drain electrode, following a shape between the source electrode and the drain electrode; and the gate electrode has one region overlapping with the source electrode and an other region overlapping with the drain electrode.Type: GrantFiled: October 17, 2011Date of Patent: December 3, 2013Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hisao Nagai, Sadayoshi Hotta, Genshiro Kawachi
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Patent number: RE44657Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.Type: GrantFiled: May 15, 2012Date of Patent: December 24, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Yutaka Shionoiri
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Patent number: RE45613Abstract: Organic transistors having a nonplanar interface between the insulating layer and the semiconductor layer are provided, along with methods for manufacturing.Type: GrantFiled: November 16, 2012Date of Patent: July 14, 2015Assignee: Tap Development Limited Liability CompanyInventors: Edwin Hirahara, David L. Lee, Richard W. Bunce