Abstract: Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.

Abstract: The present invention provides a conductive flexible substrate and a manufacture method thereof and an OLED display device and a manufacture method thereof. The conductive flexible substrate comprises a flexible substrate (1), mesh conductive lines (2) located on the flexible substrate (1) and embossing from a surface of one side of the flexible substrate (1), and a conductive layer (3) filling among the mesh conductive lines (2); a surface of one side of the flexible substrate (1) away from the mesh conductive lines (2) and the conductive layer (3) is flat. The conductive flexible substrate is capable of promoting the conductivity of the flexible substrate, and applying the conductive flexible substrate to an OLED display device can solve the issue of low conductivity of anodes in the OLED display device.

Abstract: A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract: A method of forming a semiconductor structure includes forming a first optical waveguide and a second optical waveguide on a sapphire substrate. The first optical waveguide and the second optical waveguide each include a core portion of gallium nitride (GaN), and a cladding layer laterally surrounding the core portion. The cladding layer includes a material having a refractive index less than a refractive index of the sapphire substrate. The method further includes etching a portion of the cladding layer to form a microfluidic channel therein and forming a capping layer on a top surface of the first optical waveguide, the second optical waveguide and the microfluidic channel.

Abstract: A thermal processing apparatus is provided in accordance with some embodiments. The thermal processing apparatus includes a heating source for transmitting incident radiation to a work piece having a circuit pattern formed on a front surface; a radiation sensor configured to receive light radiated from the front surface of the work piece; and a controller coupled to the radiation sensor, the controller being designed to control the heating source to reduce temperature variation of the work piece.

Abstract: A process for the production of an optoelectronic device, such as a photovoltaic cell or a light emitting diode is disclosed. The process comprises providing a substrate having a conductive coating on at least one surface, the conductive coating having an initial roughness and at least one or more spikes, and applying a functional component to the coated surface of the substrate. The surface of the substrate having the conductive coating has been subjected to a polishing step using at least one brush to reduce the height of the spikes inherent to the conductive coating and to give the conductive coating a final roughness. By reducing the spikes there is less potential for the optoelectronic device to suffer from electrical shunts which reduce the efficiency of the device.

Abstract: An optical inspection apparatus is provided which suppresses the influence of quantum noise including: light irradiator which irradiates a sample with light; reference light emitter which emits reference light; light interference unit which generates interfering light through interference between transmitted light, scattered light, or reflected light from the sample irradiated with light by the light irradiator, and the reference light emitted by the reference light emitter; light detector which detects the interfering light generated by the light interference unit; defect identifier which identifies the presence or absence of a defect based on a detection signal obtained by the light detector detecting the interfering light; and light convertor which converts at least the state of the transmitted, scattered, or reflected light from the sample, the state of the reference light emitted by the reference light emitter, or the state of the interfering light generated by the light interference unit.

Abstract: Methods for measuring a thickness of an object including acquiring at least one of a wavelength domain spectrum for an amplitude ratio (?) and a phase difference (?) of reflected light from a film material, converting the wavelength domain spectrum into a 1/wavelength domain spectrum, acquiring a resulting spectrum by performing fast fourier transform (FFT) on the 1/wavelength domain spectrum, and measuring a thickness of the film material from the resulting spectrum may be provided.

Abstract: There are provided a susceptor having a recessed wafer mounting section, in which a semiconductor wafer is mounted and which is configured to include a circular bottom portion and a side wall portion, on an upper surface, a reaction chamber in which the susceptor is provided, an imaging unit that is provided above the reaction chamber and images the semiconductor wafer and the wafer mounting section, and an image analysis unit that analyzes the deviation of the semiconductor wafer from the wafer mounting section on the basis of an image captured by the imaging unit.

Abstract: The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.

Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, directing an optical signal to a surface of the patterned photoresist layer while trimming the patterned photoresist layer, collecting a return reflected optical signal reflected from the photoresist layer, and determining a trimming endpoint by analyzing the return optical signal reflected from the photoresist layer.

Abstract: A composition for chemical mechanical polishing includes a plurality of particles and a plurality of abrasive particles. Each of the plurality of particles includes a body and a functional group. The body is configured to transfer energy of an incident light into a plasmonic wave. The functional group is configured to bind onto a metal containing layer.

Abstract: Evaluating a semiconductor wafer may include recording a first intensity of a reflection of an X-ray beam onto a test area on a substrate of the semiconductor wafer at a detector as the X-ray beam is projected substantially perpendicular to a length of expected, periodic structures in the test area and at an angle defined between the X-ray beam and a surface of the test area. Second intensities may be recorded of the reflection of the X-ray beam onto the test area as the X-ray beam is projected onto the test area at increments from the angle. Intensity peaks in the recordings of the first and second intensities are identified and, based on positions of the intensity peaks relative to the test area, a peak spacing between the plurality of expected, periodic structures is determined indicative of pitch walking or epitaxial merge.

Abstract: A solar cell includes a silicon substrate, an aluminum electrode that collects electricity from the rear surface of the silicon substrate, and a silver electrode that extracts output from the aluminum electrode. The aluminum electrode includes an opening formed on the rear surface of the silicon substrate. On a side of the opening is formed a notch that recesses parallel to the direction in which principal stress acts in a plane of the silicon substrate. The silver electrode covers at least the opening and the notch of the aluminum electrode.

Abstract: The invention relates to a method for examining a wire-sawn silicon substrate for a solar cell. The method includes irradiating the silicon substrate with an infrared radiation, detecting the infrared radiation transmitted through the silicon substrate, and analyzing the detected infrared radiation for characterizing the crystal orientation of the silicon substrate. The invention in addition relates to a device for carrying out such a method, and a method for manufacturing a solar cell.

Abstract: Apparatus for chemically etching a workpiece includes a chamber for receiving a process gas and having a pumping port for extracting exhaust gases, and a workpiece support located in the chamber upstream of the pumping port. The chamber further includes a sub-chamber located upstream of the pumping port and downstream of the workpiece support, and the sub-chamber includes a window and an excitation source, adjacent the window, for creating a plasma in a sample of the exhaust gases to create an optical emission which can be monitored through the window.

Abstract: An embodiment is an imaging apparatus including a plurality of unit cells. The imaging apparatus includes a first conductive member electrically connected to gates of the plurality of first transfer transistors, a second conductive member electrically connected to gates of the plurality of second transfer transistors, a third conductive member disposed adjacently to the first conductive member in a same wiring layer as the first conductive member and electrically connected to a plurality of nodes each included in respective one of the plurality of unit cells, and a fourth conductive member disposed adjacently to the second conductive member in a same wiring layer as the second conductive member. An opposing length of the first conductive member and the third conductive member is longer than an opposing length of the second conductive member and the fourth conductive member.

Abstract: Disclosed is a method for automatically sorting LEDs (light emitting diode) according to electrostatic resistance and a system using the same. The system includes a transport carrier for laying LEDs and passing LEDs through an electrostatic discharging zone, a lightening evaluating zone, and a sorting zone in sequence. An electrostatic discharging device discharges an electrostatic power to the LED in the electrostatic discharging zone. Furthermore, a lighting device inputs a lightening power to the LED in the lightening evaluating zone. Moreover, an evaluating device in the evaluating zone generates an evaluating signal to a sorting device in the sorting zone according to the lighting condition of the LED for allowing the sorting device to sort LEDs according to electrostatic resistance. Thereby the reliability both for the failure rate and the detection rate can be raised.

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material exposing a wafer underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.

Abstract: A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.

Abstract: Provided is a method for evaluating a solar cell incorporated into a solar module. A PL evaluation step is performed. The PL evaluation step is a step for evaluating the solar cell to be evaluated among a plurality of solar cells (10) by illuminating the solar cell (10) with light from a light source (20) and detecting the intensity of photoluminescent light (L2) emitted by the solar cell (10). The light is irradiated while a light-blocking member (21) is provided between the solar module (1) and the light source (20) so that light from the light source (20) is not incident on portions of the solar module other than the solar cell (10) to be evaluated.

Abstract: A computer readable storage medium is provided, storing a computer-executable program for causing a computer to determine at least one of mask pattern and exposure condition of an exposure apparatus having an illumination optical system for illuminating a mask with light from a light source and a projection optical system for projecting the mask pattern onto a substrate. The program causes the computer to perform calculation of an image of a pattern on an object plane of the projection optical system using information about lateral shift of an image caused by the exposure apparatus, and determination of at least one of the exposure condition and the mask pattern based on a calculation result.

Abstract: A polishing apparatus capable of monitoring an accurate progress of polishing is disclosed. The polishing apparatus includes: a polishing table for supporting a polishing pad; a table motor configured to rotate the polishing table; a top ring configured to press a substrate against the polishing pad to polish the substrate; a dresser configured to dress the polishing pad while oscillating on the polishing pad during polishing of the substrate; a filtering device configured to remove a vibration component, having a frequency corresponding to an oscillation period of the dresser, from an output current signal of the table motor; and a polishing monitoring device configured to monitor a progress of polishing of the substrate based on the output current signal from which the vibration component has been removed.

Abstract: A method for producing a substrate having an irregular concave and convex surface for scattering light includes: manufacturing a substrate having the irregular concave and convex surface; irradiating the concave and convex surface of the manufactured substrate with inspection light from a direction oblique to a normal direction and detecting returning light of the inspection light returned from the concave and convex surface by a light-receiving element provided in the normal direction of the concave and convex surface; and judging unevenness of luminance of the concave and convex surface by an image processing device based on light intensity of the returning light received. An organic EL element which includes a diffraction-grating substrate having an irregular concave and convex surface is produced with a high throughput.

Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.

Abstract: A method of manufacturing an EL display device having a light emitting part, in which a plurality of pixels are arrayed, and a thin-film transistor array device to control light emission of the light emitting part, includes a luminance measurement step of obtaining luminance data of pixel, with the light emitting part being lit. The luminance measurement step includes a first luminance measurement step and a second luminance measurement step. In the first luminance measurement step, a first imaging apparatus obtains luminance data by measuring light emission of the each pixel. The first apparatus has a resolution corresponding to that of the pixels of the light emitting part. In the second luminance measurement step after the first step, a second imaging apparatus measures light emission of a plurality of the pixels to correct the luminance data of the each pixel obtained in the first luminance measurement step. The second imaging apparatus is lower in resolution than the first imaging apparatus.

Abstract: An efficient method of detecting defects in metal patterns on the surface of wafers. Embodiments include forming a metal pattern on each of a plurality of wafers, polishing each wafer, and analyzing the surface of the metal pattern on each polished wafer for the presence of defects in the metal pattern by analyzing an optical across-wafer endpoint signal, generated at the endpoint of polishing. Embodiments include determining the location of defects in the metal pattern by determining the position of non-uniformities in the optical-across-wafer endpoint signal.

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: Disclosed are a method and system for eliminating yellow ring phenomenon occurring on the white light emitting diode (LED) based on a blue light chip exciting yellow phosphor powders and having a packaging surface enclosing thereon. Lightspot images are repeatedly acquired outside the white LED, and then each analyzed to see if the yellow ring still exists on a lightspot. If yes, a further atomization process is performed on the packaging surface of white LED, until the acquired and analyzed image shows no yellow ring exists. A lightspot-by-lightspot basis is used in the yellow ring elimination task. In the image analysis, a look up table may be provided in advanced or established at the same time simultaneously with the yellow ring elimination task. The atomization performed on the lightspot may also consider a width issue.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: Methods for chemical mechanical polishing (CMP) of semiconductor substrates, and more particularly to temperature control during such chemical mechanical polishing are provided. In one aspect, the method comprises polishing the substrate with a polishing surface during a polishing process to remove a portion of the conductive material, repeatedly monitoring a temperature of the polishing surface during the polishing process, and exposing the polishing surface to a rate quench process in response to the monitored temperature so as to achieve a target value for the monitored temperature during the polishing process.

Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Abstract: A plasma processing apparatus including: a monitor device which monitors a process quantity generated at plasma processing; a monitor value estimation unit which has monitor quantity variation models for storing change of a monitor value of the process quantity in accordance with the number of processed specimens and which estimates a monitor value for a process of a next specimen by referring to the monitor quantity variation models; and a control quantity calculation unit which stores a relation between a control quantity for controlling the process quantity of the vacuum processing device and a monitor value and which calculates the control quantity based on a deviation of the estimated monitor value from a target value to thereby control the process quantity for the process of the next specimen.

Abstract: In resin coating, carrying a light-passing member test-coated with a resin on a light-passing member carrying unit; making a light source placed above the light-passing member carrying unit emit excitation light exciting the fluorescent substance; measuring light emission characteristics of the light by irradiating the excitation light emitted from the light source unit from above to the resin coated onto the light-passing member and receiving the light that the resin emits from below the light-passing member by a light emission characteristic measurement unit; obtaining a deviation between a measurement result of the light emission characteristic measurement unit and a prescribed light emission characteristic; and deriving the appropriate resin coating quantity of the resin to be coated onto the LED element as what is used for practical production based on the deviation.

Abstract: Systems and methods are provided for developing usable chip images in order to detect and screen defects or anomalies in a manufacturing environment. More specifically, a method is provided for manufacturing at least one wafer or chip. The method includes obtaining image data of the at least one wafer or chip. The method further includes correcting the image data to remove normal variation within the image data. The method further includes comparing the corrected image data to image data for at least one other wafer or chip to determine whether the corrected image data for the at least one wafer or chip shows a defect or anomaly beyond that of the normal variation. The method further includes placing the at least one wafer or chip into a category of fabrication based on the comparison.

Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.

Abstract: A multi-patterning method of manufacturing a patterned wafer provides test structures designed to enhance overlay error measurement sensitivity for monitoring and process control. One or more patterns are overlaid on a first pattern, each of a given pitch, with the elements interleaved. Test structure is formed with elements of the overlaid patterns spaced away from respective mid-positions more closely toward elements of the first pattern. In some embodiments, test structure elements of the second pattern are overlaid midway between mid-positions of elements of the first pattern and measured by scatterometry. In other embodiments, test structure elements of the second pattern are overlaid at a slightly different pitch than the elements of the first pattern and measured by reflectivity. Measurements are compared with library measurements to identify the error, which may be fed back to control the patterning process. The multi-patterning may be formed by LELE, LLE, LFLE, or other methods.

Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.

Abstract: A whole determination area of a targeted wafer is concentrically divided in a radial direction, COP density is obtained in each divided determination segment, a maximum value of the COP density is set as COP densityRADIUSMAX, a minimum value of the COP density is set as COP densityRADIUSMIN, a value computed by “(COP densityRADIUSMAX?COP densityRADIUSMIN/COP densityRADIUSMAX” is compared to a predetermined set value, and a non-crystal-induced COP and a crystal-induced COP are distinguished from each other based on a clear criterion, thereby determining the COP generation factor. Therefore, a rejected wafer in which a determination of the crystal-induced COP is made despite being the non-crystal-induced COP can be relieved, so that a wafer production yield can be enhanced.

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract: Systems and methods are provided for developing usable chip images in order to detect and screen defects or anomalies in a manufacturing environment. More specifically, a method is provided for manufacturing at least one wafer or chip. The method includes obtaining image data of the at least one wafer or chip. The method further includes correcting the image data to remove normal variation within the image data. The method further includes comparing the corrected image data to image data for at least one other wafer or chip to determine whether the corrected image data for the at least one wafer or chip shows a defect or anomaly beyond that of the normal variation. The method further includes placing the at least one wafer or chip into a category of fabrication based on the comparison.

Abstract: A silicon carbide substrate is made of silicon carbide. In the silicon carbide substrate, a normal line of one main surface of the silicon carbide substrate and a normal line of a {03-38} plane form an angle of 0.5° or smaller in an orthogonal projection to a plane including a <01-10> direction and a <0001> direction. In this way, there can be provided the silicon carbide substrate allowing for both improvement of channel mobility of a semiconductor device and stable characteristics thereof.

Abstract: Systems and methods are provided for depositing thin patterned films of materials in which individual elements of the patterned film are deposited by two or more nozzles having different geometries. The different nozzle geometries may include one or more of different throttle diameters, different exhaust diameters, different cross-sectional shapes, different bore angles, different wall angles, different exhaust distances from the substrate, and different leading edges relative to the direction of movement of the nozzles or the substrate. Methods may include steps of ejecting a carrier gas and a material from a plurality of nozzles and depositing the material on a substrate in a plurality of laterally spaced elements.

Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes providing an organic light-emitting device including a first electrode, a second electrode and an intermediate layer including an organic emission layer, on a substrate; forming a pre-thin film encapsulation layer including an inorganic layer including a low temperature viscosity (“LVT”) inorganic material, on the organic light-emitting device; and selectively irradiating a beam having certain energy to a local area of the pre-thin film encapsulation layer.

Abstract: In an optical substrate (1), a concave-convex structure (12) including a plurality of independent convex portions (131 to 134) and concave portions (14) provided between the convex portions (131 to 134) is provided in a surface. The average interval Pave between the adjacent convex portions (131 to 134) in the concave-convex structure (12) satisfies 50 nm?Pave?1500 nm, and the convex portion (133) having a convex portion height hn satisfying 0.6 h?hn?0 h for the average convex portion height Have is present with a probability Z satisfying 1/10000?Z?1/5. When the optical substrate (1) is used in a semiconductor light-emitting element, dislocations in a semiconductor layer are dispersed to reduce the dislocation density, and thus internal quantum efficiency IQE is improved, and a waveguide mode is removed by light scattering and thus the light the extraction efficiency LEE is increased, with the result that the efficiency of light emission of the semiconductor light-emitting element is enhanced.

Abstract: A photovoltaic device is made using a method and a system disclosed herein. The method may comprise: providing a web of photovoltaic material; providing a web of interconnect material; cutting the web of photovoltaic material into a plurality of photovoltaic cells; cutting the web of interconnect material into a plurality of interconnects; providing a respective one of the plurality of interconnects between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series; and laminating the first string of photovoltaic cells which are electrically connected in series between a top laminating sheet and a bottom laminating sheet. The system may comprise: a first conveyor, an optical inspection apparatus, a removal apparatus, a sorter, a second conveyor, and an assembly apparatus configured to place an interconnect between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series.