Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: A semiconductor light emitting element including, in a light extraction layer thereof, a photonic crystal periodic structure including two systems (structures) with different refractive indices. An interface between the two systems (structures) satisfies Bragg scattering conditions, and the photonic crystal periodic structure has a photonic band gap.

Abstract: Improved pump-probe testing methods and apparatuses for measuring the performance of a plasmon element at wafer level are provided. In one embodiment, the apparatus includes a light source configured to output a first light beam on a grating located at a first end of a waveguide, the waveguide being configured to couple energy of the first light beam to the plasmon element located at a second end of the waveguide, and an optical probe assembly positioned above a top surface of the wafer. The optical probe assembly is configured to direct a second light beam on an area of the wafer including the plasmon element and detect a portion of the second light beam reflected from the area.

Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.

Abstract: The invention includes: a first process of forming a texture structure on both surfaces of a semiconductor substrate of a first conductivity type; a second process of measuring a reflectance distribution of the both surfaces of the semiconductor substrate on which the texture structure is formed; a third process of forming an impurity diffusion layer, in which an impurity element of a second conductivity type is diffused, on one of the both surfaces of the semiconductor substrate which is narrower in the reflectance distribution; a fourth process of forming, on the impurity diffusion layer, a light receiving surface-side electrode having a predetermined pattern and electrically connected to the impurity diffusion layer; and a fifth process of forming a back surface-side electrode on another of the both surfaces of the semiconductor substrate which is wider in the reflectance distribution.

Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.

Abstract: Provided is a display panel having a plurality of pixels arranged in a matrix of rows and columns. Each of the pixels is composed of a plurality of first sub-pixels emitting light of different colors. Each of the first sub-pixels is composed of a plurality of second sub-pixels emitting light of the same color. Each of the second sub-pixels includes: a first electrode; a second electrode above the first electrode; and a light-emitting layer between the first electrode and the second electrode.

Abstract: A thin overlay structure for use in imaging based metrology is disclosed. The thin overlay structure may include a first structure and second structure, the first and second structures designed to have a common center of symmetry, both structures being invariant to a 180 degree rotation about the common center of symmetry, wherein a mark region defining the extent of the structures is characterized by a first direction and a second direction orthogonal to the first direction, a length of the mark region along the first direction being greater than a length of the mark region along the second direction.

Abstract: A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.

Abstract: A manufacturing method for an organic light-emitting element includes: a first step of forming a first electrode, and forming an organic layer including a light-emitting layer; a second step of forming a second electrode, and thereby forming an element structure including the first electrode, the organic layer, and the second electrode; and a third step of performing an aging process by applying electric power between the first electrode and the second electrode in the element structure. a duration of the application of electric power in the third step is determined as the time elapsed before a time point at which a rate of decrease in a luminance of the light-emitting layer is substantially equal to a rate of decrease in a luminance of the element structure.

Abstract: Methods of characterizing semiconductor light-emitting devices (LEDs) based on product wafer characteristics are disclosed. The methods include measuring at least one product wafer characteristic, such curvature or device layer stress. The method also includes establishing a relationship between the at least one characteristic and the emission wavelengths of the LED dies formed from the product wafer. The relationship allows for predicting the emission wavelength of LED structures formed in the device layer of similarly formed product wafers. This in turn can be used to characterize the product wafers and in particular the LED structures formed thereon, and to perform process control in high-volume LED manufacturing.

Abstract: Systems and methods are provided in which individual elements of a thin patterned film are deposited by two or more nozzles having different geometries. The different nozzle geometries may include one or more of different throttle diameters, different exhaust diameters, different cross-sectional shapes, different bore angles, different wall angles, different exhaust distances from the substrate, and different leading edges relative to the direction of movement of the nozzles or the substrate. Methods may include steps of ejecting a carrier gas and a material from a plurality of nozzles and depositing the material on the substrate in a plurality of laterally spaced elements, each of the elements deposited by a separate nozzle group. At least one of the nozzles in a group of nozzles depositing an element may be configured to deposit the material on the substrate in a width that is smaller than the width of the element.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).

Abstract: An apparatus for removing a defect according to the embodiment includes an image processing part for observing a surface of a substrate; a layer forming part for forming a layer on the surface of the substrate; and a humidity controlling part for controlling humidity in a chamber in which the substrate is placed. A method for removing a defect according to the embodiment includes detecting the defect on a surface of a substrate; forming an oxide layer by oxidizing the defect; and removing the oxide layer. A method for removing a defect according to another embodiment includes forming an oxide layer on an entire surface of a substrate; and removing the oxide layer to remove the defect.

Abstract: The process for growing at least one semiconductor nanowire (3), said growth process comprising a step of forming, on a substrate (1), a nucleation layer (2) for the growth of the nanowire (3) and a step of growth of the nanowire (3). The step of formation of the nucleation layer (2) comprises the following steps: deposition onto the substrate (1) of a layer of a transition metal (4) chosen from Ti, V, Cr, Zr, Nb, Mo, Hf, Ta; nitridation of at least a part (2) of the transition metal layer so as to form a transition metal nitride layer having a surface intended for growing the nanowire (3).

Abstract: The present disclosure provides a system for fabricating a semiconductor device. The system includes a semiconductor fabrication tool. The semiconductor fabrication tool has an integrated inter interface that measures a first process parameter of the fabrication tool. The system also includes a wireless sensor. The wireless sensor is detachably coupled to the fabrication tool. The wireless sensor measures a second process parameter of the fabrication tool. The second process parameter is different from the first process parameter.

Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.

Abstract: A three-dimensional integrated circuit device includes a first substrate having a first crystal orientation comprising at least one or more PMOS devices thereon and a first dielectric layer overlying the one or more PMOS devices. The three-dimensional integrated circuit device also includes a second substrate having a second crystal orientation comprising at least one or more NMOS devices thereon; and a second dielectric layer overlying the one or more NMOS devices. An interface region couples the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.

Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract: Detecting residue of a filler material over a patterned underlying layer includes causing relative motion between a probe of an optical metrology system and a substrate, obtaining a plurality of measured spectra with the optical metrology system through the probe from a plurality of different measurement spots within an area on the substrate, comparing each of the plurality of measured spectra to a reference spectrum to generate a plurality of similarity values, the reference spectrum being a spectrum reflected from the filler material, combining the similarity values to generate a scalar value, and determining the presence of residue based on the scalar value.

Abstract: Methods and apparatus for method for characterizing a height profile of a scattering surface relative to a fiducial plane. The scattering surface, which may be an interface between distinct solid, liquid, gaseous or plasma phases, is illuminated with substantially spatially coherent light, and light scattered by the scattering surface is collected and dispersed, such as by a grating, into zeroth- and first-order beams. A spatial Fourier transform of the zeroth- and first-order beams is created, and one of the beams is low-pass filtered. The beams are interfered at a focal plane detector to generate an interferogram, which is transformed to retrieve a spatially resolved quantitative phase image and/or an amplitude image of the scattering surface. Imaging may be performed during an etching process, and may be used to adaptively control a photoetching process in a feedback loop.

Abstract: The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface.

Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: An apparatus for performing metrology of a wafer. The apparatus may include a substrate with a plurality of microprobes. A plurality of light sources may direct light onto each of the microprobes. Light reflected from the microprobes may be detected by a plurality of photodetectors thereby generating a detection signal associated with each of the microprobes. A controller may send a driving signal to each of the plurality of microprobes and determine a height profile and a surface charge profile of the wafer based on each of the detection signals.

Abstract: The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.

Abstract: A method for calculating an offset value for aligned deposition of a second pattern onto a first pattern, comprising steps of: (a) loading a substrate with the first pattern on a surface of the substrate into a pattern recognition device at an original position inside the pattern recognition device; (b) determining a coordinate of a prescribed point of the first pattern by the pattern recognition device; (c) superimposing the second pattern onto the first pattern on the surface of the substrate; (d) bringing back the substrate with the first pattern and the second pattern into the original position inside the pattern recognition device; (e) determining a coordinate of a prescribed point of the second pattern by the pattern recognition device; wherein the prescribed point of the first pattern corresponds to the prescribed point of the second pattern; and (f) calculating the offset value between the first pattern and the second pattern.

Abstract: Provided is a method and a device for measuring a temperature which can recognize the temperature of a semiconductor layer directly with high precision when the semiconductor layer is formed by deposition. The quantity of laser light transmitted to a semiconductor layer is monitored by a photodetector by using laser light having a wavelength ?s at which the transmittance of light changes abruptly when the temperature of the semiconductor layer reaches Ts during or after deposition. When heat being given to the semiconductor layer is changed, the quantity of laser light monitored by the photodetector changes abruptly when the temperature of the semiconductor layer reaches Ts at a time A, B or C. Consequently, the fact that the temperature of the semiconductor layer reached Ts at a time A, B or C can be recognized exactly, and an error in temperature information observed by a device for measuring temperature variations can be calibrated, for example.

Abstract: Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

Abstract: A defect inspection system is disclosed for easily setting inspection conditions and providing an inspection condition and a defect signal intensity to an operator. The defect inspection system digitizes a defective image, and a reference image corresponding thereto and a mismatched portion of the defective image and the reference image as a defect signal intensity and accumulates them in association with the inspection condition. The inspection conditions are changed to repeat evaluations while repeating accumulating works until the evaluation of all the inspection conditions in a set range is completed. A recipe file including the accumulated conditions having the high defect signal intensity and an inspection condition item distribution as a inspection condition recipe is automatically outputted and provided to the operator.

Abstract: The invention provides a measurement of lateral diffusion of implanted ions in the doped well regions of semiconductor devices comprising: designing a test model having active areas, the P-type and N-type doped well regions of the active areas are separated by STI, and the bottom width of the STI is determined; performing multiple processes on the test model comprising the ion implantation process and the tungsten interconnection process to simulate a semiconductor device structure, wherein during the ion implantation process, in the P-type or N-type doped well regions, only the first procedure of the ion implantation process is performed; scanning the test model, obtaining a light-dark pattern of the tungsten interconnects. The present invention is convenient and accessible and can provide reference to optimize the property of the doped well regions of the semiconductor devices and ensure the yield enhancement.

Abstract: Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.

Abstract: A defect inspection device for a silicon wafer comprises: an infrared light illumination which illuminates the silicon wafer with a light power that has been adjusted in accordance with a specific resistance value of the silicon wafer; and an imaging unit constituted by a line sensor array that is sensitive to infrared light, which captures the silicon wafer.

Abstract: An object is to provide a method for manufacturing a light-emitting device in which a defective portion is insulated. In addition, another object is to provide a manufacturing apparatus of a light-emitting device in which a defective portion is insulated. After a hemispherical lens is formed to overlap with a light-emitting element, the defective portion is detected. Then, the hemispherical lens overlapping with the light-emitting element including the detected defective portion may be irradiated with a laser beam having a low energy density, and the defective portion may be insulated by light condensed through the hemispherical lens.

Abstract: Provided is a substrate processing apparatus in which flexibility of disposing a device configured to determine a holding state of a substrate and the flexibility of timing of determining the holding state are enhanced. The substrate processing apparatus includes a light projector configured to radiate detection light toward a region where a substrate may exist when the substrate is held by a substrate holding member and a light receiver configured to receive the detection light radiated from the light projector. A light path of the detection light from the light projector toward the light receiver passes a substrate surrounding member installed around the substrate held by the substrate holding member. The detection light penetrates the substrate surrounding member and has a wavelength which does not penetrate the substrate.

Abstract: Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described.

Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.

Abstract: Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.

Abstract: A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate.

Abstract: Disclosed is a method for removing individual layers of a layer stack. The layer stack includes a semiconductor layer disposed onto an optically dense electrically conductive layer which in turn is disposed upon an optically transparent layer. A laser at a first power level is projected through the optically transparent layer and onto the optically dense electrically conductive layer. The semiconductor layer is removed through heat evaporation imparted by the laser at the first power level without removing the optically dense electrically conductive layer. Optionally, the laser at a second power level, which is greater than the first power level, is projected onto the optically dense electrically conductive layer through the optically transparent layer. The optically dense electrically conductive layer is removed through heat evaporation imparted by the laser at the second power level without removing the optically transparent layer.

Abstract: An apparatus for depositing and inspecting an organic light emitting display panel includes a depositor part configured to deposit thin film layers on a panel, the thin film layers including an anode layer, an organic film layer, and a cathode layer, and an inspector part configured to measure spectra of light reflected from the thin film layers, compare the measured spectra to reference spectra, and determine thickness correctness of individual thin film layers.

Abstract: Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

Abstract: A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 ?m in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×104 per 1 cm2. Accordingly, reverse leakage current can be reduced.

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract: A method for manufacturing a semiconductor laser includes the steps of preparing a mold with a pattern surface having recesses, forming a stacked semiconductor layer including a grating layer, forming a resin part on the grating layer, forming a resin pattern portion on the resin part, forming a diffraction grating by etching the grating layer using the resin part as a mask, and forming a mesa-structure on the stacked semiconductor layer. Each of the recesses includes two end portions and a middle portion between the two end portions. A depth of at least one of the two end portions from the pattern surface is greater than that of the middle portion. The step of forming the mesa-structure includes the step of etching the stacked semiconductor layer so as to remove end portions of the diffraction grating in a direction orthogonal to a periodic direction thereof.