Abstract: Apparatus for monitoring a thickness of a silicon wafer with a highly-doped layer at least at a backside of the silicon wafer is provided. The apparatus has a source configured to emit coherent light of multiple wavelengths. Moreover, the apparatus comprises a measuring head configured to be contactlessly positioned adjacent the silicon wafer and configured to illuminate at least a portion of the silicon wafer with the coherent light and to receive at least a portion of radiation reflected by the silicon wafer. Additionally, the apparatus comprises a spectrometer, a beam splitter and an evaluation device. The evaluation device is configured to determine a thickness of the silicon wafer by analyzing the radiation reflected by the silicon wafer by an optical coherence tomography process. The coherent light is emitted multiple wavelengths in a bandwidth b around a central wavelength wc.

Abstract: Provided is a substrate processing apparatus in which flexibility of disposing a device configured to determine a holding state of a substrate and the flexibility of timing of determining the holding state are enhanced. The substrate processing apparatus includes a light projector configured to radiate detection light toward a region where a substrate may exist when the substrate is held by a substrate holding member and a light receiver configured to receive the detection light radiated from the light projector. A light path of the detection light from the light projector toward the light receiver passes a substrate surrounding member installed around the substrate held by the substrate holding member. The detection light penetrates the substrate surrounding member and has a wavelength which does not penetrate the substrate.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a silicon carbide substrate having a first main surface and a second main surface. On the first main surface, an electrode is formed. The silicon carbide substrate has a hexagonal crystal structure. The first main surface has an off angle of ±8° or smaller relative to a {0001} plane. The first main surface has such a property that when irradiated with excitation light having energy equal to or greater than a band gap of silicon carbide, luminous regions in a wavelength range of 750 nm or greater are generated in the first main surface at a density of 1×104 cm?2 or smaller. In this way, a yield of a silicon carbide semiconductor device can be improved.

Abstract: Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.

Abstract: In a plasma processing method and apparatus for processing a film to be processed contained in a film structure preliminarily formed on an upper surface of a wafer mounted in a processing chamber, by using plasma, a residual film thickness at an arbitrary time is calculated using a result of comparing detective differential waveform pattern data with actual differential waveform pattern data. The detective differential waveform pattern data is produced by using two basic differential waveform pattern data which respectively use, as parameters, residual thicknesses of the films to be processed in film structures having underlying films with different thicknesses and the wavelengths of the interference light. The detective waveform pattern data being preliminarily prepared prior to processing of the wafer. Determination is made as to whether or not an object of the processing has been reached by using the residual film thickness.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.

Abstract: Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer.

Abstract: Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process.

Abstract: The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.

Abstract: A method and apparatus are disclosed which use a photoluminescent light intensity signature to characterize a processed photovoltaic substrate.

Abstract: Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In2Se3 and In2S3.

Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Abstract: The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges.

Abstract: A method of manufacturing a light-emitting device includes forming wave length conversion portion on a light-emitting element. The light emitting device includes a light-emitting element which emits light of a predetermined wavelength and a wavelength conversion portion which includes a fluorescent substance which is excited by the light emitted from the light-emitting element so as to emit fluorescence of a wavelength different from the predetermined wavelength, which wavelength conversion portion is formed by including the fluorescent substance, a layered silicate mineral, and an organometallic compound.

Abstract: A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes.

Abstract: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.

Abstract: Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing an adjustable or optimized laser patterning process to form openings with different geometry in a passivation layer disposed on a substrate based on different film properties in the passivation layer and the substrate. In one embodiment, a method of forming a solar cell includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, performing a substrate inspection process by a detector disposed in the laser patterning apparatus, determining a laser patterning recipe configured to form openings in the passivation layer based on information obtained from the substrate inspection process, and performing a laser patterning process on the passivation layer using the determined laser patterning recipe.

Abstract: Provided is a TFT board for a liquid crystal display device including: a circuit layer formed on a substrate, the circuit layer including a thin film transistor including a semiconductor layer, a gate electrode, a drain electrode, and a source electrode; and a color filter layer formed on the circuit layer. The color filter layer has a through hole formed therein above the semiconductor layer in a region between the source electrode and the drain electrode.

Abstract: A measuring method and device for characterizing a semiconductor component (1) having a pn junction and a measuring surface, which has a contacting subarea, covered by a metallization. The method including: A. Planar application of electromagnetic excitation radiation onto the measuring area of the semiconductor component (1) for separating charge carrier pairs in the semiconductor component (1), and B. spatially resolved measurement of electromagnetic radiation originating from the semiconductor component (1) using a detection unit. In one step A, a predetermined excitation subarea of the measuring surface has a predetermined intensity of the excitation radiation and at least one sink subarea of the measuring surface has an intensity of the excitation radiation which is less than the intensity applied to the excitation subarea. The excitation and sink subareas are disposed on opposite sides of said contacting subarea and adjoin it and/or entirely or partially overlap it.

Abstract: Provided is a method of manufacturing a semiconductor device, which includes the steps of: (a) preparing a processing target including a wafer (21) and a protective member (24) formed on the wafer (21); (b) measuring a thickness of the protective member (24) at a plurality of points; and (c) setting a desired value of a total thickness of the wafer (21) and the protective member (24) based on measurement results at the plurality of points to grind the wafer (21) in accordance with the desired value.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.

Abstract: A method of aligning a semiconductor chip includes forming a semiconductor chip with a light-activated circuit including at least one photosite, positioning the semiconductor chip relative to a device, and illuminating the positioned semiconductor chip. The method further includes generating an RF signal with an RF circuit based upon illumination of the at least one photosite, and determining the position of the photosite with respect to the device based upon the generated RF signal.

Abstract: A process for preparing a subassembly, the process comprising: (a) defining the location of one or more grooves for receiving optical conduits on the top planar surface of a wafer or panel, the grooves corresponding to multiple interposers on the wafer or panel; and (b) etching the grooves into the wafer or panel, each groove having sidewalls and first and second terminal ends and a first facet at each terminal end perpendicular to the side walls, each first facet having a first angle relative to the top planar surface, each groove being shared by a pair of transmitting and receiving interposers on the wafer or panel prior to being diced such that the first and second terminal ends of each groove correspond to transmitting and receiving interposers, respectively.

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a reflection film. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a bonding material. The bonding material integrates the fluorescent materials. The reflection film is partially provided on the fluorescent material layer and has a higher reflectance to the radiated light of the light emitting layer than to the radiated light of the fluorescent materials.

Abstract: Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.

Abstract: An inspection method for a semiconductor light-emitting device includes an image capturing step for capturing an image of photoluminescence released from the active layer, an inspection region extracting step for extracting an inspection region from the captured image; a luminance average determination step for, determining the semiconductor light emitting device as defective when a luminance average is smaller than a predetermined threshold, a luminance variance determination step for determining the semiconductor light emitting device as defective when a luminance variance is larger than a predetermined threshold, a color determination step for determining the semiconductor light-emitting device as defective when a pixel in which a color component indicating a photoluminescence intensity of light released from the active layer and having a wavelength shorter than the original emitting wavelength, and a total determination step for totally determining the semiconductor light-emitting device as defective when

Abstract: A temperature-adjusted spectrometer can include a light source and a temperature sensor.

Abstract: The invention provides a semiconductor device and a method of automatically inspecting the appearance, which achieves proper recognition of the size of a chipping occurring from an end portion of the semiconductor device toward the element forming region by an automatic appearance inspection machine, and prevents a problem of judging an appearance non-defective product as an appearance defective product. A semiconductor device includes a resin layer extending from an element forming region over a guard ring surrounding the element forming region so as to cover these except a plurality of portions of the guard ring, and a chipping extending from a chip end portion of a semiconductor device toward the end portion of the resin layer.

Abstract: A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a spray chamber that, during operation, is urged in a sealing manner onto a sealing plate holding the integrated circuit under test. The atomized mist cools the integrated circuit and then condenses on the spray chamber wall. The condensed fluid is pumped out of the chamber and is circulated in a chiller, so as to be re-circulated and injected again into the micro-spray heads. The pressure inside the spray chamber may be controlled to provide a desired boiling point.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.

Abstract: A donor layer that is formed by performing a heat treatment for a crystal defect formed by proton radiation is provided in an n-type drift layer of an n? semiconductor substrate. The donor layer has an impurity concentration distribution including a portion with the maximum impurity concentration and a portion with a concentration gradient in which the impurity concentration is reduce to the same impurity concentration as that of the n-type drift layer in a direction from the portion with the maximum impurity concentration to both surfaces of the n-type drift layer. The crystal defect formed in the n-type drift layer is a composite crystal defect mainly caused by a vacancy, oxygen, and hydrogen.

Abstract: A method is described for obtaining information for use in modeling of a lithographic process. A pattern feature is formed on a target portion of a substrate by projecting a beam of radiation onto the target portion of the substrate. For that target portion the lithographic process is characterized by one or both of a first property that varies in a first direction along a surface of the substrate, and a second property that varies in a second direction along a surface of the substrate. A property of the pattern feature is measured. Using the measured property of the pattern feature and at least one of the first and second properties, information is obtained for use in modeling the process. The lithographic process may be or include the projection of the beam of radiation onto the surface of the substrate.

Abstract: A method for testing a conductive web includes moving a conductive web past at least one electrostatic probe, providing an alternating current or voltage which generates an alternating current to the at least one electrostatic probe, measuring a current or voltage in the at least one electrostatic probe induced by a capacitance between the conductive web and the at least one electrostatic probe, comparing the measured current or voltage to a reference value, and determining a level of bagginess of the conductive web based on the step of comparing.

Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.

Abstract: Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations.

Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Abstract: To improve the performance of a semiconductor device, a semiconductor device manufacturing method includes an exposing process of performing pattern exposure of a resist film formed on a substrate by using EUV light reflected from a front surface of an EUV mask as a reflective mask. In this exposing process, the resist film is subjected to pattern exposure by repeating a process of irradiating the resist film with the EUV light by changing a focal position of the EUV light with which the resist film is irradiated, along a film thickness direction of the resist film. After this exposing process, the resist film subjected to pattern exposure is developed to form a resist pattern.

Abstract: Provided is a luminance measurement method for accurately measuring luminance of each pixel even if pixel images of a display panel overlap each other on an imaging surface of a camera. Pixels of a display panel are imaged by a solid-state imaging camera. One or more pixels are turned on and imaged such that pixel images do not overlap each other on an imaging surface. A central exposure factor indicating luminance of the central part of the pixel image is calculated based on a picture element output corresponding to the central part. A peripheral exposure factor indicating luminance of the peripheral part of the pixel image is calculated based on a picture element output corresponding to the peripheral part. All pixels are turned on and imaged, and luminance of all pixels is calculated based on this imaged image, the central exposure factor, and the peripheral exposure factor.

Abstract: According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.

Abstract: A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask 109 is applied to the recorded image and unmasked portions 111 of the image are further processed by averaging. The unmasked portions 111 are selected such that they include memory portions of the wafer.

Abstract: An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy.

Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.

Abstract: A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters.

Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.

Abstract: A probe includes a contact member brought into contact with an object to be tested. Contact particles having conductivity are uniformly distributed in the contact member. A part of the contact particles protrude from a surface of the contact member on the side of the object to be tested. A conductive member having elasticity is placed on a surface of the contact member on the opposite side to the object to be tested. The probe further includes an insulating sheet including a through hole and the contact member is so positioned as to penetrate the through hole. An upper part of the contact member is formed of a conductor which does not include the contact particles. An additional conductor is placed on a surface of the conductor on the side opposite to the object to be tested.

Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.

Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.