Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/257)
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Patent number: 10528862Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.Type: GrantFiled: December 17, 2018Date of Patent: January 7, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee
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Patent number: 10515971Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.Type: GrantFiled: December 11, 2017Date of Patent: December 24, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Ankit Kumar, Manoj Kumar, Chia-Hao Lee
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Patent number: 10510610Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: GrantFiled: March 28, 2018Date of Patent: December 17, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
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Patent number: 10510544Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.Type: GrantFiled: October 5, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ling Hsu, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Shihkuang Yang
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Patent number: 10475993Abstract: In fabricating a radio frequency (RF) switch, a heat spreader is provided and a heating element is deposited. A thermally conductive and electrically insulating material is deposited over the heating element. The heating element and the thermally conductive and electrically insulating material are patterned, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A layer of an upper dielectric is deposited. A conformability support layer is optionally deposited over the upper dielectric and the thermally conductive and electrically insulating material. A phase-change material is deposited over the optional conformability support layer and the underlying upper dielectric and the thermally conductive and electrically insulating material.Type: GrantFiled: August 14, 2018Date of Patent: November 12, 2019Assignee: Newport Fab, LLCInventors: Gregory P. Slovin, Jefferson E. Rose, David J. Howard, Michael J. DeBar, Nabil El-Hinnawy
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Patent number: 10468496Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.Type: GrantFiled: October 23, 2017Date of Patent: November 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Hisada, Koichi Arai
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Patent number: 10468259Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.Type: GrantFiled: April 30, 2018Date of Patent: November 5, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Vinod Robert Purayath, Nitin K. Ingle
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Patent number: 10446559Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.Type: GrantFiled: August 2, 2018Date of Patent: October 15, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Chao-An Liu, Ching-Hsiang Chang, Yi-Wei Chen
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Patent number: 10431577Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: GrantFiled: February 9, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Kenneth W. Marr
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Patent number: 10411139Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.Type: GrantFiled: July 22, 2017Date of Patent: September 10, 2019Assignee: Renesas Electronics CorporationInventor: Tomohiro Yamashita
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Patent number: 10388605Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.Type: GrantFiled: April 30, 2018Date of Patent: August 20, 2019Assignee: SK hynix Inc.Inventors: Tae Kyung Kim, Chul Young Park, Hyoung Soon Yune
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Patent number: 10283566Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.Type: GrantFiled: June 1, 2017Date of Patent: May 7, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jongsun Sel, Tuan Pham, Mitsuteru Mushiga, Yoshihiro Ikeda, Daewung Kang, Akio Nishida
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Patent number: 10269823Abstract: The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.Type: GrantFiled: April 19, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Yuan Chang, Chia-Ping Lai
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Patent number: 10249629Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.Type: GrantFiled: January 22, 2018Date of Patent: April 2, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Chieh-Te Chen, Hsien-Shih Chu
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Patent number: 10224413Abstract: A radio-frequency (RF) carbon-nanotube (CNT) field effect transistor (FET) device. The device includes a source contact, a drain contact, semi-conducting CNTs positioned between the source and drain contacts, high-? gate dielectric, and a local backgate positioned below the semi-conducting CNTs, in which the local backgate is capable of RF performance and is capable of being used in a backgate burnout process used to enhance the semiconducting to metallic tube ratio of the device.Type: GrantFiled: January 30, 2012Date of Patent: March 5, 2019Assignee: Northrop Grumman Systems CorporationInventors: Joseph A. Payne, Wayne S. Miller, Monica P. Lilly, Silai V. Krishnaswamy
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Patent number: 10211213Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A selection gate electrode is formed over a semiconductor substrate via a first insulation film. Over the opposite side surfaces of the selection gate electrode, second insulation films of sidewall insulation films are formed. Over the semiconductor substrate, a memory gate electrode is formed via a third insulation film having a charge accumulation part. The selection gate electrode and the memory gate electrode are adjacent to each other via the second insulation film and the third insulation film. The second insulation film is not formed under the memory gate electrode. The total thickness of the second insulation film and the third insulation film interposed between the selection gate electrode and the memory gate electrode is larger than the thickness of the third insulation film interposed between the semiconductor substrate and the memory gate electrode.Type: GrantFiled: November 22, 2015Date of Patent: February 19, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuyoshi Mihara
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Patent number: 10170484Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.Type: GrantFiled: October 18, 2017Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Min Gyu Sung, Ruilong Xie, Bipul C. Paul
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Patent number: 10163721Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.Type: GrantFiled: September 28, 2017Date of Patent: December 25, 2018Assignee: International Business Machines CorporationInventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu
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Patent number: 10115721Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.Type: GrantFiled: May 27, 2016Date of Patent: October 30, 2018Assignee: INTEL CORPORATIONInventors: Walid M. Hafez, Peter J Vandervoorn, Chia-Hong Jan
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Patent number: 10109631Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.Type: GrantFiled: February 21, 2017Date of Patent: October 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
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Patent number: 10103160Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.Type: GrantFiled: February 2, 2016Date of Patent: October 16, 2018Assignee: Micron Technology, Inc.Inventors: Srikant Jayanti, Fatma Arzum Simsek-Ege, Pavan Kumar Reddy Aella
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Patent number: 10103162Abstract: Provided is a vertical neuromorphic devices stacked structure comprising a main gate which is formed on a substrate and has a vertical pillar shape, a main gate insulating layer stack formed on outer side surface of the main gate; a semiconductor region formed on outer side surface of the main gate insulating layer stack, a plurality of electrode layers formed on the side surface of the semiconductor region, a plurality of control gates formed on the side surface of the semiconductor region; and a plurality of control gate insulating layer stacks which are surrounding surfaces of the control gates and are formed between the control gate and the semiconductor region, and between the control gate and the electrode layer, and wherein the electrode layers and the control gates surrounded by the control gate insulating layer stack are stacked sequentially and alternately on the side surface of the semiconductor region.Type: GrantFiled: July 27, 2016Date of Patent: October 16, 2018Assignee: SNU R&DB FOUNDATIONInventors: Jong-Ho Lee, Chul-Heung Kim, Suhwan Lim
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Patent number: 10090328Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.Type: GrantFiled: February 10, 2017Date of Patent: October 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Junggil Yang, Dong Il Bae, Geumjong Bae, Seungmin Song, Jongho Lee
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Patent number: 10043713Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.Type: GrantFiled: May 10, 2017Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Xinyuan Dou, Hong Yu, Zhenyu Hu, Xing Zhang
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Patent number: 10038139Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.Type: GrantFiled: May 2, 2016Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Chih-Yang Chang, Yu-Wen Liao
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Patent number: 10026622Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.Type: GrantFiled: August 31, 2016Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mitsuhiro Omura, Tsubasa Imamura, Itsuko Sakai
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Patent number: 10020198Abstract: The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes forming a polysilicon stripe over a semiconductor fin, forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe, forming a raised source/drain region in the semiconductor fin, and forming a carbonitride etch stop layer surrounding the nitride sidewall spacer.Type: GrantFiled: December 15, 2016Date of Patent: July 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shiang-Bau Wang, Victor Y. Lu
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Patent number: 9997641Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.Type: GrantFiled: February 23, 2016Date of Patent: June 12, 2018Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
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Patent number: 9997524Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.Type: GrantFiled: September 21, 2016Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Tsun-Kai Tsao, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
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Patent number: 9947864Abstract: In one embodiment, a method for etching a workpiece including a lower electrode and a multi-layer film disposed on the lower electrode, the multi-layer film including a first magnetic layer, a second magnetic layer, and an insulating layer interposed between the first magnetic layer and the second magnetic layer, through a mask, is provided. The method includes exposing the workpiece to plasma of first processing gas which contains first rare gas and second rare gas having an atomic number larger than that of the first rare gas, and does not contain hydrogen gas.Type: GrantFiled: August 6, 2015Date of Patent: April 17, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Tamotsu Morimoto, Song yun Kang
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Patent number: 9882018Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.Type: GrantFiled: May 15, 2015Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Young Jin Noh, Jae Ho Choi, Bio Kim, Kwang Min Park, Jae Young Ahn, Dong Chul Yoo, Seung Hyun Lim, Jeon Il Lee
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Patent number: 9882030Abstract: A method for manufacturing a fin-type semiconductor device includes providing a semiconductor structure comprising a plurality of fins, and a plurality of trenches each disposed between two adjacent fins, filling each of the trenches with a spacer, and performing a first dopant implantation into the spacer to form an etch stop layer. The thus formed etch stop layer can decrease the etch rate of the HF/SiCoNi etchant towards oxide, e.g., silicon oxide, thereby reducing the spacer loss in a subsequent HF/SiCoNi etch of the dummy gate insulation layer, and improving the device performance.Type: GrantFiled: August 12, 2016Date of Patent: January 30, 2018Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 9865332Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.Type: GrantFiled: January 20, 2016Date of Patent: January 9, 2018Assignee: Zeno Semiconductor, Inc.Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
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Patent number: 9837603Abstract: Encapsulation of the magnetoresistive device after formation protects the sidewalls of the magnetoresistive device from degradation during subsequent deposition of interlayer dielectric material. The encapsulation also helps prevent short circuits between the top electrode of the magnetoresistive device and underlying layers within the magnetoresistive device. The encapsulation can be accomplished by depositing a layer of encapsulating material after device formation, where an etch back operation selectively removes the portions of the layer of encapsulating material other than the material on the sidewalls of the magnetoresistive device.Type: GrantFiled: October 12, 2016Date of Patent: December 5, 2017Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
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Patent number: 9831258Abstract: A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.Type: GrantFiled: June 15, 2017Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventor: Tatsuyoshi Mihara
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Patent number: 9825046Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.Type: GrantFiled: January 5, 2016Date of Patent: November 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chu Lin, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu
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Patent number: 9825036Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate; two fins extending from the substrate and through the isolation structure; a gate stack engaging channel regions of the two fins; a dielectric layer disposed over the isolation structure and adjacent to S/D regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. The lower portions of the four S/D features are surrounded at least partially by the dielectric layer. The upper portions of the four S/D features merge into two merged second S/D features with one on each side of the gate stack. Each of the two merged S/D features has a curvy top surface.Type: GrantFiled: February 23, 2016Date of Patent: November 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu
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Patent number: 9806129Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.Type: GrantFiled: February 25, 2014Date of Patent: October 31, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Marcello Ravasio, Samuele Sciarrillo, Fabio Pellizzer, Innocenzo Tortorelli, Roberto Somaschini, Cristina Casellato, Riccardo Mottadelli
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Patent number: 9768183Abstract: An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.Type: GrantFiled: May 15, 2015Date of Patent: September 19, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Akimoto, Hidetoshi Nakamoto, Keita Kumamoto, Hidehito Koseki, Yuji Takahashi, Noritaka Fukuo, Tomoyasu Kakegawa, Takuya Futase
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Patent number: 9755143Abstract: A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.Type: GrantFiled: August 8, 2014Date of Patent: September 5, 2017Assignee: CROSSBAR, INC.Inventor: Scott Brad Herner
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Patent number: 9754780Abstract: A manufacturing method of a semiconductor device includes generating hydrogen radicals by plasma excitation of hydrogen gas and exposing a surface of a substrate on which silicon and metal are exposed to a reducing atmosphere created with the hydrogen radicals, and generating hydrogen radicals and hydroxyl radicals by plasma excitation of a mixed gas of hydrogen gas and oxygen-containing gas and oxidizing the silicon exposed on the surface of the substrate by exposing the surface of the substrate to the hydrogen radicals and hydroxyl radicals to obtain the substrate on which the metal and oxidized silicon are formed.Type: GrantFiled: December 1, 2015Date of Patent: September 5, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
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Patent number: 9748240Abstract: A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in the first semiconductor-region along the boundary and are electrically connected to the first semiconductor-region. Second contacts are located in the second semiconductor-region along the boundary and are electrically connected to the second semiconductor-region. The second contacts are not located in parts of the second semiconductor-region on an opposite side to the first contacts across the boundary. The parts of the second semiconductor-region are adjacent to the first contacts in a first direction s perpendicular to an arranging direction of the first and second contacts. The first contacts are not located in parts of the first semiconductor-region on an opposite side to the second contacts across the boundary. The parts of the first semiconductor-region are adjacent to second contacts in the first direction.Type: GrantFiled: February 17, 2016Date of Patent: August 29, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tetsuaki Utsumi
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Patent number: 9698149Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.Type: GrantFiled: January 13, 2015Date of Patent: July 4, 2017Assignee: SanDisk Technologies LLCInventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
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Patent number: 9673208Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.Type: GrantFiled: September 13, 2016Date of Patent: June 6, 2017Assignee: Silicon Storage Technology, Inc.Inventors: Jinho Kim, Chien-Sheng Su, Feng Zhou, Xian Liu, Nhan Do, Prateep Tuntasood, Parviz Ghazavi
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Patent number: 9660177Abstract: An improved method for etching a magnetic tunneling junction (MTJ) structure is achieved. A stack of MTJ layers is provided on a bottom electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage or sidewall redeposition is formed on sidewalls of the MTJ device. A dielectric layer is deposited on the MTJ device and the bottom electrode. The dielectric layer is etched away using ion beam etching at an angle relative to vertical of greater than 50 degrees wherein the dielectric layer on the sidewalls is etched away and wherein sidewall damage or sidewall redeposition is also removed and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.Type: GrantFiled: September 9, 2015Date of Patent: May 23, 2017Assignee: Headway Technologies, Inc.Inventors: Rao Annapragada, Yu-Jen Wang, Dongna Shen
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Patent number: 9653289Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.Type: GrantFiled: September 19, 2016Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9653547Abstract: A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.Type: GrantFiled: March 17, 2016Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
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Patent number: 9646718Abstract: A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device.Type: GrantFiled: March 3, 2015Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-wook Park, Ki-won Park
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Patent number: 9640432Abstract: The disclosed subject matter provides a memory device structure and a fabricating method thereof. The memory device structure includes a substrate including a device region and a peripheral region; multiple gate structures; a first dielectric layer, a second barrier layer, multiple source interconnecting lines, and multiple drain region plugs; a second dielectric layer in the device region include multiple source line plugs, and multiple second drain region plugs, and multiple controlling gate plugs; a third dielectric layer including multiple first conductive layers; a fourth dielectric layer including multiple interconnecting structures; a fifth dielectric layer including multiple second conductive layers; and a sixth dielectric layer including multiple third conductive layers.Type: GrantFiled: June 13, 2016Date of Patent: May 2, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Jinshuang Zhang, Shaobin Li, Sheng-Fen Chiu
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Patent number: 9608115Abstract: FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.Type: GrantFiled: July 25, 2016Date of Patent: March 28, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Deyuan Xiao