Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.

Abstract: Numerous other aspects are provided a method for making a nonvolatile memory cell. The method includes forming a non-planar dielectric structure, and conformally depositing a semiconductor layer over the dielectric structure. A portion of the semiconductor layer serves as a channel region for a transistor, and the channel region is non-planar in shape.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

Abstract: A semiconductor device includes an element isolation region having an element isolation insulating film therein; an active region delineated by the element isolation region; agate insulating film formed in the active region; a charge storage layer above the gate insulating film; and an interelectrode insulating film. The interelectrode insulating film is formed in a first region above an upper surface of the element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a stack of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film. A control electrode layer is formed above the interelectrode insulating film. The second silicon oxide film is thinner in the first region than in the third region.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).

Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.

Abstract: A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.

Abstract: The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.

Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.

Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.

Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract: A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.

Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.

Abstract: A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.

Abstract: The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described.

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.

Abstract: According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (VR/VW-generator) is located on a separate peripheral-circuit die. The VR/VW-generator generates at least a read and/or write voltage to the 3D-array die. A single VR/VW-generator die can support multiple 3D-array dies.

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract: A semiconductor memory device and the operating method thereof use a low pass voltage to boost a channel of unselected cell strings during a program operation, and boost the channel of the cell string by using the GIDL phenomenon, thereby reducing a disturbance influence on the memory cells connected to the unselected cell strings due to a high pass voltage.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.

Abstract: A method of manufacturing an interconnection member includes forming on a substrate a wettability changing layer containing a material in which critical surface tension is changed by giving energy; forming a depression part in the wettability changing layer by a laser ablation method using a laser of an ultraviolet region; and coating the depression part with an electrically conductive ink to form an electrically conductive part. At the same time when a pattern of the depression part is formed in the wettability changing layer, a pattern of a high surface energy area is formed as a result of the critical surface tension being changed.

Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

Abstract: A semiconductor device includes an interlayer insulating layer on a substrate, and a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including a DC hole exposing the substrate, an insulating DC spacer on an inner wall of the DC hole, and a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.