Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.

Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Abstract: A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

Abstract: A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.

Abstract: A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of storing at least one charge. The charge storage elements can include fullerenes.

Abstract: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer.

Abstract: Provided is a method of forming a floating gate, a non-volatile memory device using the same, and a method of fabricating the non-volatile memory device, in which nano-crystals of nano-size whose density and size can be easily adjusted, are synthesized using micelles so as to be used as the floating gate of the non-volatile memory device. The floating gate is fabricated by forming a tunnel oxide film on the semiconductor substrate, coating a gate formation solution on the tunnel oxide film in which the gate formation solution includes micelle templates into which precursors capable of synthesizing metallic salts in nano-structures formed by a self-assembly method are introduced, and arranging the metallic salts on the tunnel oxide film by removing the micelle templates, to thereby form the floating gate.

Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor.

Abstract: Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.

Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

Abstract: A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide.

Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.

Abstract: A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: The present invention relates to an electrode 100 with high capacitance. The electrode includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15. The nano-sized structures are concave-shaped and are of a size in the range from 2 nanometers to 50 nanometers. The nano-sized structures are configured for increasing specific surface area of the electrode. The present invention also provides a method for making the above-described electrode. The method includes steps of providing a conducting substrate, forming a number of nano-sized structures on the conducting substrate, and forming a coating on the nano-sized structures.

Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.

Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.

Abstract: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.

Abstract: Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word lines aligned at each sidewall of the source line to cross over the active region in parallel with the source line; and a charge storage layer interposed between the word lines and the active region. Since the word lines are formed at both sides of the source line using an anisotropic etch-back process, without photolithography, the area of a unit cell can be reduced.

Abstract: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.

Abstract: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.

Abstract: An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

Abstract: A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Abstract: A coupling oxide film is formed on a silicon substrate, a polysilicon film is further formed thereupon, and a low-temperature oxide film is deposited to a thickness of 10 nm, for example. Next, a silicon nitride film is formed on this low-temperature oxide film, and selectively removed by dry etching. At this time, the low-temperature oxide film serves as an etching stopper film, so the low-temperature oxide film and polysilicon film are not over-etched. Subsequently, the polysilicon film is dry-etched, forming a recess. A floating gate is then formed of the polysilicon film.

Abstract: A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.

Abstract: Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.

Abstract: A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.

Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: A non-volatile semiconductor memory device has a gate insulating film formed on a semiconductor substrate between isolation regions, a first gate electrode formed on the gate insulating film, an intergate insulating film formed on the first gate electrode, and a second gate electrode formed on the intergate insulating film. The first gate electrode has a first part positioned between isolation insulating films, a second part positioned on the first part and having a partial portion positioned on the isolation region, and a third part positioned on the second part. A width of the third part is set narrower than that of the second part.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A silicon nitride film for storing electric charge is formed on a semiconductor substrate while placing a tunnel oxide film in between, and the silicon nitride film is then subjected to hydrogen plasma treatment so as to effectively erase unnecessary charge stored therein during various process steps in fabrication of the semiconductor memory device, to thereby stabilize the threshold voltage (Vth) of the semiconductor memory device.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 ? to about 200 ?.

Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.