Abstract: A structure of a stacked gate of a flash memory cell and a method for forming the same is disclosed. A semiconductor substrate having a first conductive gate structure, wherein the first gate conductive structure is disposed in between two neighboring raised shallow trench isolation structures, the dielectric pillar disposed on the sidewall of the first gate conductive structure having a top surface level higher than a top surface of the first gate conductive structure, formed thereon. A conformal conductive layer is formed over the said structure. The conductive layer is patterned to form a second gate conductive structure. The first and the second gate conductive structures forms a floating gate. Next, a thin dielectric layer is formed over the floating gate structure, then another conductive layer is formed over the dielectric layer, and the said conductive layer is patterned to form a control gate.

Abstract: Disclosed is a method for semiconductor device planarization. The semiconductor manufacturing method includes a memory region and a logic device region, comprising steps of: a) forming first patterns on each regions of the memory and the logic device, respectively; b) forming a first interlayer insulating layer on the memory region and on the logic device region, respectively; c) forming a second pattern on the first inter-layer insulating layer in the memory region; d) forming a second interlayer insulating layer on the memory region and on the logic device region, respectively; e) polishing the second interlayer insulating layer; f) forming a planarization insulating layer on the memory region and on the logic device region; g) removing the planarization insulating layer on the memory region through a selectively etching process; and h) planarizing the memory region and the logic device region through a polishing process.

Abstract: There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a cylindrical shape is formed within the hole and the control gate is formed within the floating gate. Therefore, the source used as a current supply and the silicon substrate may be formed integratedly, and also the process of forming a device separation film can be omitted, thus allowing manufacturing an ultra high integration non-volatile memory device.

Abstract: A memory device, a manufacturing method thereof, and an integrated circuit thereof are provided for storing information over a long period of time even if the memory device is manufactured at low temperatures. On a substrate made of glass, etc., a memory transistor and a selection transistor are formed, with a silicon nitride film and a silicon dioxide film in between. The memory transistor and the selection transistor are connected in series at a second impurity region. The conduction region for memory of the memory transistor is made of non-single crystal silicon and a storage region comprises a plurality of dispersed particulates made of non-single crystal silicon. Therefore, electrical charges can be stored partially if a tunnel insulating film has any defects. The tunnel insulating film is formed by exposing the surface of the conduction region for memory to the ionized gas containing oxygen atoms.

Abstract: The present invention relates to a method of manufacturing a flash memory device. According to the present invention, a dielectric film is formed and an amorphous silicon layer is then formed to mitigate a topology generated by patterning of a first polysilicon layer in a cell region. The amorphous silicon layer serves as a protection layer of the dielectric film in the cell region when a gate oxide film in a peripheral circuit region is formed. Therefore, the present invention can not only improve the resistance of a word line in the cell region but also improve the film quality of the dielectric film and the gate oxide film in the peripheral circuit region.

Abstract: The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.

Abstract: A field transistor for electrostatic discharge (ESD) protection and method for making such a transistor is described. The field transistor includes a gate conductive layer pattern formed on a field oxide layer. Since the gate conductive layer pattern is formed on the field oxide layer, a thin gate insulating layer having a high possibility of insulation breakdown is not used. To form an inversion layer for providing a current path between source and drain regions, a field oxide layer is interposed to form low concentration source and drain regions overlapped by the gate conductive layer pattern.

Abstract: A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for generating trapped charges are formed through using poly-edge discharge techniques wherein the gate structures of the memory cells are laterally separated from the vertical region of the source and drain regions. The gate structure forms a laterally directed e-field through the charge trapping layer to one of the source and drain regions which enables the charge to be trapped and retained in an area that is lateral to the source and drain regions. Lateral separation of the gate from the source and drain regions is maintained through the use of spacers which may take the form of insulated polysilicon structures or in an alternate embodiment may take the form of insulating spacers located on the sidewalls of the gate structure.

Abstract: An electrically programmable memory cell is of the type having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate. The floating gate and the control gate are made by a self-aligned method wherein, a first layer of silicon dioxide is provided on the substrate. A first layer of polysilicon is then provided on the first layer of silicon dioxide. The first layer of polysilicon is patterned and selective portions are removed. A second layer of silicon dioxide is provided on the patterned first layer of polysilicon. Portions of the second layer of silicon dioxide are selectively masked to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of silicon dioxide is anisotropically etched. The second layer of silicon dioxide is then isotropically etched. The first layer of polysilicon is anisotropically etched to defined the floating gate.

Abstract: A process for forming an aerosol of semiconductor nanoparticles includes pyrolyzing a semiconductor material-containing gas then quenching the gas being pyrolyzed to control particle size and prevent uncontrolled coagulation. The aerosol is heated to densify the particles and form crystalline nanoparticles. In an exemplary embodiment, the crystalline particles are advantageously classified by size using a differential mobility analyzer and particles having diameters outside of a pre-selected range of sizes, are removed from the aerosol. In an exemplary embodiment, the crystalline, classified and densified nanoparticles are oxidized to form a continuous oxide shell over the semiconductor core of the particles. The cores include a density which approaches the bulk density of the pure material of which the cores are composed and the majority of the particle cores are single crystalline. The oxidized particles are deposited on a substrate using thermophoretic, electrophoretic, or other deposition means.

Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

Abstract: Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desirable semiconductor dots to be produced, and allowing production of the memory devices having a multi-dot floating gate with ease and at low costs even when a substrate is made of glass or plastic.

Abstract: A method of forming a tunnel oxide layer of a non-volatile memory cell is disclosed. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. After patterning the second dielectric layer to form an opening, the semiconductor substrate is oxidized to form a non-tunnel oxide within the opening. After removing the second dielectric layer, source/drain regions are formed by performing an ion implantation process and an annealing process. After removing the first dielectric layer, an HSG layer with a plurality of HSG grains are formed on the source/drain regions. After that, the HSG layer is partially etched by HF vapor to enlarge a spacing between the HSG grains. Finally, the HSG layer is oxidized to form the tunnel oxide layer.

Abstract: A semiconductor device and its manufacturing method which not only can solve the problem that a memory cell size determines a write/erase speed of memory cell transistors but also can increase the write/erase speed while preventing the reduction in the reliability of an insulating film between a control gate and a second-layer floating gate. Since the insulating film under a second-layer floating gate has irregularity, the second-layer floating gate itself has irregularity, whereby its surface area and hence the write/erase speed is increased. Further, since the insulating film under the second-layer floating gate has irregularity, protrusions on the surface of the second-layer floating gate are rounded. Therefore, the degree of electric field concentration is reduced, whereby the reliability of the insulating film between the control gate and the second-layer floating gate is prevented from being lowered.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A semiconductor device includes a substrate and an oxide layer disposed outwardly from the substrate. The semiconductor device also includes a polysilicon layer disposed outwardly from the oxide layer, the oxide layer having an interface between the oxide layer and the polysilicon layer, the interface having asperities such that the barrier potential between the polysilicon layer and the substrate is reduced in response to the asperities.

Abstract: A method of forming a tunnel oxide layer of a non-volatile memory cell is disclosed. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. After patterning the second dielectric layer to form an opening, the semiconductor substrate is oxidized to form a non-tunnel oxide within the opening. After removing the second dielectric layer, source/drain regions are formed by performing an ion implantation process and an annealing process. After removing the first dielectric layer, an HSG layer with a plurality of HSG grains are formed on the source/drain regions. After that, the HSG layer is partially etched by HF vapor to enlarge a spacing between the HSG grains. Finally, the HSG layer is oxidized to form the tunnel oxide layer.

Abstract: In a semiconductor memory device, such as a flash memory device, a conductor layer of metal or metal compound having high refractoriness, such as titanium nitride, is formed on a conductor or wiring formed by a buried diffusion layer to reduce resistance thereof. In the present invention, such conductor layer is formed by using small number of process steps and without using photolithography process. For example, after forming the buried diffusion layer for source and drain regions by ion implantation using each floating gate and dummy gate as a mask, titanium nitride is deposited throughout a substrate. Thereafter, by using oxide film growth and etching back process, an oxide film layer remaining on the titanium nitride layer between the floating gate and the dummy gate is fabricated. Then, the titanium nitride layer on the floating gate and on the dummy gate is removed by using this remained oxide film layer as a mask, without using any photolithography process.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate.

Abstract: Disclosed is an EEPROM device, and a method of making such a device, which incorporates a self-aligned tunnel window having acceptably low gate capacitance at the tunnel oxide node, and which avoids the defects caused by field oxide induced stresses in the tunnel oxide. The EEPROM of the present invention includes a semiconductor substrate with a doped memory diffusion region. Overlying at least a portion of the memory diffusion is a tunnel oxide. Overlying at least a portion of the tunnel oxide is a floating gate structure including an extension. The tunnel window of the EEPROM of the present invention is defined within at least a portion of the tunnel oxide and having at least two edges defined by the floating gate extension, so that when a defined voltage is applied to the memory diffusion a tunnel current sufficient to change the state of the EEPROM flows between the memory diffusion and the floating gate structure.

Abstract: Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide in the NO-DPCC diagram including a series of steps that permit the removal of the oxide in two distinct moments from the matrix area and from the circuitry area. In this manner the active circuitry areas are preserved from the danger of breaking the tunnel oxide, thus avoiding the degradation of the quality of the oxides and increasing, in addition, the level of reliability of the device itself.

Abstract: A hemispherical grain (HSG) formation process for enlarging the surface area of a capacitor electrode, wherein stable, defect-free HSG, having outstanding selectivity, is formed. An amorphous silicon layer, which constitutes a capacitor electrode, is formed on an Si wafer, on which is formed a silicon-based dielectric layer, which constitutes an interlevel dielectric layer. An HSG layer, in which there exists practically no defects, is formed on the amorphous silicon layer at a crystal nuclei formation temperature of under 620° C. Further, in accordance with properly controlling the crystal nuclei formation temperature, and the flow rate of monosilane (SiH4), which is supplied for crystal nuclei formation, it is possible to furnish selectivity such that HSG nuclei are formed solely on the amorphous silicon layer, without being formed on a silicon-based dielectric layer.

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.

Abstract: A method for achieving improved piezoelectric films for use in a resonator device is disclosed. The method is based on applicant's recognition that the texture of a piezoelectric film (e.g., as used in a piezoelectric resonator) is directly affected by the surface morphology of the underlying electrode, and additionally, the surface morphology of the electrode is affected by the surface morphology of the underlying oxide layer or Bragg stack. Accordingly, the invention comprises a method of making a device having a piezoelectric film and electrode comprising controlling the deposition and surface roughness of the electrode and optionally, the Bragg stack.

Abstract: A method of forming a generally conformal iridium layer (preferably, an iridium metal layer optionally containing oxides of iridium) on a substrate, such as a semiconductor wafer, using complexes of the formula CpIr(CO)2 wherein Cp is a substituted or unsubstituted cyclopentadienyl ligand; and forming a generally conformal iridium layer on a surface of the substrate, wherein the layer is formed from the precursor composition in the presence of one or more carrier gases and one or more oxidizing gases.

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/Si02) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs).

Abstract: A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate.

Abstract: The present invention relates to a method of forming a charge injection region on a floating gate of a memory cell using an etching process. The present invention defines the sharp corners for electron charge injection region of a floating gate by etching the shape into the floating gate silicon rather than forming the injection point using an oxidation process. By using the etching process of the present invention, limitations on the size of the floating gate are overcome and the memory cell can be formed using the minimum geometry allowed by lithography. This allows further scaling of the cell film thickness than is presently capable and does not limit the choice of insulator film materials.

Abstract: In one aspect of the invention, an amorphous layer of silicon is provided which has a gradient of thickness variation. The amorphous layer of silicon is transformed into a hemispherical grain polysilicon layer that has varying grain size therein. In another aspect of the invention, a material is provided and has an upper surface and inwardly tapered openings. A first electrically conductive electrode layer is formed within the openings and includes a plurality of hemispherical grain polysilicon layers. At least one of the hemispherical grain polysilicon layers has a grain size gradient defined by a smaller grain size in a region proximate the upper surface and a larger grain size beneath the region with the smaller grain size. An electrically insulative layer is formed over the first electrode layer and a second electrically conductive electrode layer is formed over the electrically insulative layer.

Abstract: While a storage region 15 has of many dispersed particulates (dots) (15a), the surface density of the particulates (15a) is set to be higher than that of structural holes (pin holes) produced in a tunnel insulating film (14a), or the number of the particulates (15a) in the storage region (15) is set to five or more. While a conduction region (13c) is formed by a polysilicon layer (13) having a surface roughness of 0.1 nm to 100 nm, the number of the particulates (15a) in the storage region (15) is set to be larger than the number of crystal grains in the conduction region (13c). Even when a defect such as a pin hole occurs in the tunnel insulating film (14a) and charges stored in a part of the particulates are leaked, the charges stored in the particulates formed in a region where no defect occurs are not leaked. Thus, information can be held for a long time.

Abstract: The present invention relates to flash memory cell and fabricating method therefor, including a semiconductor substrate having first typed impurity, a first gate insulating layer on a first certain part of the semiconductor substrate, a buried insulating layer on a second certain part of the semiconductor substrate, the buried insulating layer being connected to the first gate insulating layer, a floating gate on the first gate insulating layer wherein the floating gate extends on and is overlapped with the buried insulating layer in part, a second gate insulating layer on the floating gate, a third gate insulating layer at a lateral surface of the floating gate, a control gate on the second gate insulating layer wherein one side of the control gate corresponds to that of the floating gate and the other side of the control gate does not correspond to that of the control gate and the one side of said control gate overlaps over the buried insulating layer, a fourth gate insulating layer on the control gate, an

Abstract: The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/SiO2) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs).

Abstract: In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including a number of memory cells each having a floating gate and a control gate, an interlayer insulator film is formed to cover the control gate of the memory cells in the memory zone and a gate electrode formed in the peripheral circuit zone. A contact hole is formed through the interlayer insulator film to reach the gate electrode formed in the peripheral circuit zone, and is filled with a first conducting material. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate of a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line.

Abstract: In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.

Abstract: Provided is a method for fabricating a high dielectric capacitor of a semiconductor device without decreasing the properties of the dielectric under oxygen atmosphere in the process for depositing a high dielectric thin film at high temperature and the thermal treatment process for the crystallization of the dielectric. By using the hybrid electrode of the IrO2 film and the Pt or Ir film together with properties of diffusion barrier and bottom electrode, the present invention can enhance the thermal stability of the bottom electrode and, thus, fabricate a capacitor with excellent properties through stabilization of the processes for forming the high dielectric film.

Abstract: A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is then removed. A polysilicon film is deposited over the substrate 2 and then oxidized into sacrificial oxide layer. After stripping the sacrificial oxide layer, a rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. After the pad oxide film is removed, an undoped silicon film is deposited over the substrate 2 and then etched back by a dry etching. A rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: A met for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a thin, undoped HSG-Si film is deposited. A wet etching process is performed to etch back by HNO3/CH3COOH/HF/DI, or phosphoric acid (HPO3). The topography of the doped substrate region is then become rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Abstract: A method is provided for fabricating a tunneling oxide layer over a semiconductor substrate with a textured surface. The method is suitable for a semiconductor substrate, such as a silicon substrate, having a polysilicon layer formed over the substrate. The method has several steps of performing a thermal oxidation process to over oxidize the polysilicon layer so as to form an interfacial oxide layer between the substrate and the polysilicon layer, which actually is oxidized as an oxide layer. Due to material property of polysilicon, a textured surface is naturally formed on a top of the substrate. After removing the oxide layer and the interfacial oxide layer, a tunneling oxide layer is formed over the substrate with the textured surface.

Abstract: A method of fabricating a semiconductor memory device comprises the steps of: (a) forming an interlayer insulating film on a semiconductor substrate, opening a contact hole in said interlayer insulating film, and burying a plug in said contact hole; (b) forming a first insulating film on said interlayer insulating film inclusive of said plug, and forming a trench in said first insulating film above said plug; (c) forming a first conductive film on said first insulating film inclusive of said trench, and etching back said first conductive film by a chemical mechanical polishing method to form a bottom electrode inside said trench; (d) forming a high dielectric film or a ferroelectric film and a second conductive film in this order on said first insulating film inclusive of said bottom electrode; and (e) patterning simultaneously said high dielectric film or ferroelectric film and said second conductive film to form a capacitor insulating film and a top electrode.

Abstract: A process for a split-gate transistor (e.g. flash-EEPROM cell), which includes a channel's drain-area, a first insulator disposed over the drain-area and a first gate disposed over the first insulator, and a control (select) gate is insulatively disposed over the channel's source-area and over a channel's gap-area located between the drain area and source area.It includes growing a second thin thermal oxide to be in contact with the first gate and the channel's source-area and gap-area that is adjacent he channel's drain-area, depositing TEOS based LPCVD oxide on the second oxide and then depositing the control gate on the first gate and over the channel's source and gap areas.It prevents the formation of an oxide beak under the first gate, thereby the first insulator has a uniform thickness. The polysilicon of the control gate conforms to the side wall of the first gate and does not protrude under the first gate.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.