Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.

Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: A method of manufacturing a graphene electronic device may include forming a metal compound layer and a catalyst layer on a substrate, the catalyst layer including a metal element in the metal compound layer, growing a graphene layer on the catalyst layer, and converting the catalyst layer into a portion of the metal compound layer.

Abstract: Disclosed is a method of forming a vertical pillar-type field effect transistor (FET). One or more semiconductor pillars are formed by epitaxial deposition in one or more openings, respectively, that extend through a first dielectric layer and that have high aspect ratios in two directions. The first dielectric layer is etched back and the following components are formed laterally surrounding the semiconductor pillar(s): a first source/drain region above and adjacent to the first dielectric layer, a second dielectric layer on the first source/drain region, a gate on the second dielectric layer and a gate cap on the gate. The gate cap extends over the top surface(s) of the semiconductor pillar(s). A recess is formed in the gate cap to expose at least the top surface(s) of the semiconductor pillar(s) and a second source/drain region is formed within the recess. Also disclosed is the vertical pillar-type FET structure.

Abstract: The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.

Abstract: A semiconductor device includes a semiconductor layer, having a drain region, a body region, and a source region, a gate electrode, facing the body region via a gate insulating film, a first pillar layer disposed inside the semiconductor layer so as to be continuous to the body region, and a trap level region, disposed inside the semiconductor layer and containing charged particles that form a trap level, and an electric field concentration portion, where an electric field concentrates in an off state in which a channel is not formed in the body region, and the trap level region are disposed at mutually different depth positions in a depth direction of the first pillar layer.

Abstract: During a fabrication of a semiconductor device, a recess is created in a substrate material disposed along a direction of a plane of fabrication. A layer of a removable material is formed in the recess. A bottom layer is formed above the layer of removable material. A vertical channel above the bottom layer is formed in a direction substantially orthogonal to the direction of the plane of fabrication. A gate is formed using a metal above the bottom layer and relative to the vertical channel. A tunnel is created under the bottom layer by removing the removable material from under the bottom layer such that the backside of the bottom layer forms a ceiling of the tunnel. The tunnel is filled using a conductive material such that the conductive material makes electrical contact with the backside of the bottom layer.

Abstract: A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. The semiconductor device may include a hole source layer interposed between the conductive layer and the sub-channel layer. The semiconductor device may include source select lines located over the sub-channel layer. The semiconductor device may include source channel layers contacting the sub-channel layer by penetrating the source select lines.

Abstract: The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction.

Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.

Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.

Abstract: An integrated circuit and method are disclosed. In the method, a stack of sacrificial layers is formed on a semiconductor layer such that a first portion of the stack has an extra sacrificial layer as compared to a second portion. First and second multi-layer fins are etched through the first and second portions and into the semiconductor layer. First and second vertical field effect transistors (VFETs) are formed using the fins. During VFET formation, multiple etch processes are performed to remove the sacrificial layers. The last of these etch processes is a selective isotropic etch process that removes the extra sacrificial layer and etches back first and second upper dielectric spacers on the first and second multi-layer fins. Due to the extra sacrificial layer, the first upper dielectric spacer will be taller than the second and the first VFET will have a higher threshold voltage than the second.

Abstract: A semiconductor device includes a layer having first and second surfaces and a first type first region, a second type second region in the layer between the first region and first surface, a first type third region in the layer between the second region and first surface, first and second gate electrodes, wherein the second region is between the first and second gate electrodes, a first field plate electrode between the second surface and first gate electrode, a second field plate electrode between the second surface and second gate electrode, a first film, at least a portion between the first field plate electrode and first region, a second film at least a portion between the second field plate electrode and first region, and a second type fourth region in the first region between the first and second films. A portion of the first region is between second and fourth regions.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Abstract: A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region.

Abstract: A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

Abstract: A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. A gate length in a first direction of a floating gate positioned between one of the electrode layers and the semiconductor layer is longer than a layer thickness in the first direction of the one of the electrode layers. A ratio of the layer thickness of the one of the electrode layers to the gate length has a positive correlation with an outer diameter of a first portion of the semiconductor layer surrounded by the floating gate in a second direction from the semiconductor layer toward the one of the electrode layers.

Abstract: A semiconductor structure is provided that includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a first device region and a second device region. First vertically stacked and suspended nanosheets of semiconductor channel material of the first crystallographic orientation are located above the substrate and within the first device region. Second vertically stacked and suspended nanosheets of semiconductor channel material of a second crystallographic orientation are located above the substrate and within the second device region. In accordance with the present application, the second crystallographic orientation is different from the first crystallographic orientation.

Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

Abstract: A lateral double diffused MOS transistor including a substrate, a source region and a drain region disposed in the substrate, a first contact and a second contact connected to the source region and the drain region, respectively, a gate insulation layer and a gate electrode on the substrate, a first field plate extending from the gate electrode toward the drain region, a coupling gate disposed between the second contact and the first field plate on the substrate, the coupling gate having a coupling voltage by coupling operation with the second contact, and a second field plate disposed between the coupling gate and the first field plate on the substrate, the second field plate being electrically connected to the second field plate.

Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.

Abstract: A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor body, a first doped region, a second doped region, a gate and a dielectric layer. The semiconductor body is disposed on a dielectric substrate and has a protrusion portion, a first portion and a second portion. The first portion and the second portion are respectively disposed at two opposite sides of the protrusion portion. The first doped region is disposed in a top of the protrusion portion. The second doped region is disposed in an end of the first portion far away from the protrusion portion. The gate is disposed on the first portion and adjacent to the protrusion portion. The dielectric layer is disposed between the gate and the protrusion portion, and between the gate and the first portion.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate. The vertical FET comprises a lower source/drain region disposed on the substrate. The lower source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface, wherein the bottom surface of the lower source/drain region contacts the substrate. A lower metallic contact is disposed adjacent to, and in contact with, at least one sidewall surface of the lower source/drain region, wherein the lower metallic contact comprises a laterally extended portion which laterally extends from the at least one sidewall surface of the lower source/drain region.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

Abstract: A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.

Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

Abstract: A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion. The method also includes forming a sacrificial layer disposed over the fin device structure and forming a device semiconductor layer disposed over a surface of the sacrificial layer. A gate dielectric layer is then formed and is disposed over a surface of the device semiconductor layer. A gate electrode layer is formed and disposed over a surface of the gate dielectric layer. The method includes removing a portion of the sacrificial layer to form a cavity surrounding the fin structure and performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure.

Abstract: An integrated circuit for demagnetizing an inductive load includes a first switch to control current supplied by a voltage supply to the inductive load. A Zener diode includes an anode connected to a control terminal of the first switch and a cathode connected to the voltage supply. A second switch includes a control terminal and first and second terminals. A temperature sensing circuit is configured to sense a temperature of the first switch and to generate a sensed temperature. A comparing circuit includes inputs that receive a reference temperature and the sensed temperature and an output connected to the control terminal of the second switch.

Abstract: A method for producing a semiconductor device includes forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first pillar-shaped silicon layer is formed in an upper portion of the first fin-shaped silicon layer, and a second pillar-shaped silicon layer is formed in an upper portion of the second fin-shaped silicon layer.

Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.

Abstract: A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins.

Abstract: Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n?-type epitaxial layer, and formation of an n-type impurity region and p-type impurity region that form an n-type region and p-type region of a parallel p-n layer, are repeatedly carried out. Furthermore, an n?-type counter region is formed in the vicinity of the p-type impurity region in the uppermost n?-type epitaxial layer forming the parallel p-n layer. Next, an n?-type epitaxial layer is deposited on the n?-type epitaxial layer. Next, a MOS gate structure is formed in the n?-type epitaxial layer. At this time, when carrying out a p-type base region diffusion process, the n-type and p-type impurity regions are caused to diffuse, thereby forming the n-type region and p-type region of the parallel p-n layer.

Abstract: Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: A method to make a semiconductor device, a first SiO2 layer and a first Si3N4 layer are sequentially formed on the semiconductor substrate. The first SiO2 layer and the first Si3N4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process. After this, a second SiO2 layer and a second Si3N4 layer are formed conformal onto the substrate. Anisotropic etching is then performed to remove the second Si3N4 and second SiO2 layer except on the trench sidewall. Then a thermal oxidation process is done to grow oxide only in trench bottom and at trench top corner. The radius of curvature of trench bottom and trench top corner is increased at the same time by this thermal oxidation process.