V-gate Patents (Class 438/271)
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Patent number: 8105902Abstract: A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.Type: GrantFiled: June 27, 2009Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jong-Han Shin
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Patent number: 8088660Abstract: A method for producing an electrode in a semiconductor layer includes providing a substrate with a first surface and a second surface, forming a first trench having sidewalls and extending into the substrate from the first surface and forming a plug in the first trench. The method further includes reducing a thickness of the semiconductor substrate by removing semiconductor material beginning at the first surface so as to at least partially uncover sidewalls of the plug and forming a semiconductor layer on the semiconductor substrate, the semiconductor layer at least partially covering the uncovered sidewalls of the plug, and having an upper surface.Type: GrantFiled: December 15, 2010Date of Patent: January 3, 2012Assignee: Infineon Technologies Austria AGInventors: Ralf Siemieniec, Martin Henning Vielemeyer, Oliver Blank
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Patent number: 8084865Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.Type: GrantFiled: April 30, 2008Date of Patent: December 27, 2011Assignee: Infineon Technologies AGInventors: Franz Hirler, Walter Rieger, Uwe Schmalzbauer, Rudolf Zelsacher, Markus Zundel
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Patent number: 8080459Abstract: A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.Type: GrantFiled: June 15, 2004Date of Patent: December 20, 2011Assignee: Vishay-SiliconixInventor: Robert Q. Xu
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Patent number: 8048742Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.Type: GrantFiled: June 29, 2007Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
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Patent number: 7989295Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.Type: GrantFiled: January 26, 2011Date of Patent: August 2, 2011Assignee: Nissan Motor Co., Ltd.Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
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Patent number: 7951673Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.Type: GrantFiled: February 26, 2010Date of Patent: May 31, 2011Assignee: Intel CorporationInventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
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Patent number: 7927952Abstract: A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.Type: GrantFiled: May 28, 2008Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 7923327Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.Type: GrantFiled: June 24, 2008Date of Patent: April 12, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sung Kun Park
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Patent number: 7910983Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.Type: GrantFiled: September 30, 2008Date of Patent: March 22, 2011Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Michael Treu
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Patent number: 7859017Abstract: A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer.Type: GrantFiled: September 23, 2009Date of Patent: December 28, 2010Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Publication number: 20100314682Abstract: This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.Type: ApplicationFiled: March 5, 2010Publication date: December 16, 2010Inventors: Hamza Yilmaz, Madhur Bobde, Yeeheng Lee, Lingpeng Guan, Xiaobin Wang, John Chen, Anup Bhalla
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Patent number: 7842572Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.Type: GrantFiled: August 3, 2009Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Yong-chul Oh, Makoto Yoshida
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Patent number: 7843020Abstract: A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.Type: GrantFiled: September 24, 2007Date of Patent: November 30, 2010Assignee: Sharp Kabushiki KaishaInventor: Keiji Hayashi
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Patent number: 7816210Abstract: A method is disclosed for producing a trench transistor which has at least two trenches with in each case a field electrode arranged therein and a gate electrode arranged therein. In the method, it is provided to implement the trenches with different trench widths and then to produce the field electrodes by filling up the trenches with an electrode material and subsequent cutting back of the electrode material. The different trench width leads to different etching rates during the cutting back of the electrode material, and thus to field electrodes which are spaced apart from a top edge of the trenches by different amounts. Following this, the gate electrodes are produced which, due to the different dimensions of the field electrodes, extend into the trenches to a different depth, resulting in different gate capacitances for the gate electrodes in the two trenches.Type: GrantFiled: August 30, 2006Date of Patent: October 19, 2010Assignee: Infineon Technologies AGInventors: Martin Poelzl, Franz Hirler
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Patent number: 7816728Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: GrantFiled: April 12, 2005Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Jack A. Mandelman, Tak H. Ning, Yoichi Otani
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Patent number: 7800187Abstract: In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a width larger than the uniform width. A bottom of a base region adjacent to the trench is adjacent to the second opening.Type: GrantFiled: May 18, 2006Date of Patent: September 21, 2010Assignee: NEC Electronics CorporationInventor: Naoki Matsuura
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Patent number: 7790551Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.Type: GrantFiled: October 22, 2009Date of Patent: September 7, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7728380Abstract: Embodiments relate to a semiconductor device. In embodiments, a semiconductor device may include a semiconductor substrate having isolation layers and a well region, a gate electrode formed within a trench having a predetermined depth in the well region, source/drain regions formed at both sides of the trench, respectively, an interlayer dielectric layer formed on the semiconductor substrate to have predetermined contact holes, and metal interconnections formed within the contact holes, respectively.Type: GrantFiled: December 26, 2006Date of Patent: June 1, 2010Assignee: Dongbu HiTek Co., LtdInventor: Jae Hwan Shim
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Patent number: 7704833Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.Type: GrantFiled: August 25, 2004Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
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Patent number: 7696599Abstract: A trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).Type: GrantFiled: November 26, 2004Date of Patent: April 13, 2010Assignee: NXP B.V.Inventors: Raymond J. E. Hueting, Erwin A. Hijzen
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Patent number: 7691699Abstract: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.Type: GrantFiled: December 30, 2005Date of Patent: April 6, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Patent number: 7678653Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: February 16, 2009Date of Patent: March 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7675114Abstract: In order to obtain an increased avalanche strength, a trench transistor is proposed in which the breakdown location is defined in a trench bottom region below body contact zones. This is done by means of a modulation of the dopant concentration in a drift zone and an insulation layer thickness modulation in the bottom region of the trenches.Type: GrantFiled: March 30, 2006Date of Patent: March 9, 2010Assignee: Infineon Technologies AGInventor: Markus Zundel
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Patent number: 7670911Abstract: A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film, forming a lower impurity diffusion region, removing the silicon oxide film to expose a silicon side of the protrusion-like region, thermally oxidizing the silicon side to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film, forming a gate electrode over a side of the protrusion-like region, and forming an upper impurity diffusion region.Type: GrantFiled: July 31, 2008Date of Patent: March 2, 2010Assignee: Elpida Memory, Inc.Inventor: Kiyonori Oyu
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Patent number: 7666733Abstract: According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a, 77b) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.Type: GrantFiled: December 4, 2007Date of Patent: February 23, 2010Assignee: Commissariat a l'Energie AtomiqueInventor: Simon Deleonibus
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Patent number: 7648878Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.Type: GrantFiled: December 20, 2005Date of Patent: January 19, 2010Assignee: Hynix Semiconductor Inc.Inventor: Tae-Woo Jung
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Patent number: 7622350Abstract: A method of manufacturing a semiconductor device is provided. Device separation portions defining first, second and third regions are formed in a substrate. A recess is formed at the first region. An N-type well is formed at the third region. An N-type polysilicon layer is formed at the first and second regions. A P-type polysilicon layer is formed at the third region. At least one of metal silicide film and a metal film is formed on the N-type polysilicon layer and the P-type polysilicon layer. Etching is performed to form a gate electrode including the N-type polysilicon layer at the first and second regions and a gate electrode including the P-type polysilicon layer at the third region. A cell transistor having a recess channel structure is formed at the first region, an nMOSFET structure is formed at the second region, and a pMOSFET structure is formed at the third region.Type: GrantFiled: October 23, 2008Date of Patent: November 24, 2009Assignee: Elpida Memory Inc.Inventor: Yasushi Yamazaki
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Patent number: 7615452Abstract: A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer.Type: GrantFiled: July 1, 2008Date of Patent: November 10, 2009Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 7615472Abstract: A method for manufacturing a nitride semiconductor substrate includes the steps of growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.Type: GrantFiled: June 8, 2009Date of Patent: November 10, 2009Assignee: Nichia CorporationInventor: Toru Takasone
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Publication number: 20090269896Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.Type: ApplicationFiled: April 24, 2008Publication date: October 29, 2009Inventors: Hui Chen, Qi Wang, Briant Harward, James Pan
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Publication number: 20090179258Abstract: A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided on the first layer and an n-type region formed on a part of the second layer, and having a wall surface extending over the first layer, a body region of the second layer other than the n-type region and the n-type region; a gate insulating film formed such that the gate insulating film is opposed to the body region on the wall surface; a gate electrode formed such that the gate electrode is opposed to the body region through the gate insulating film; a source electrode formed such that the source electrode is electrically connected to the n-type region; a drain electrode formed such that the drain electrode is electrically connected to the first layer; and a body electrode formed such that the body electrode is electrically connected to the body region.Type: ApplicationFiled: December 23, 2008Publication date: July 16, 2009Applicant: ROHM CO., LTD.Inventor: Hirotaka OTAKE
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Patent number: 7553731Abstract: A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.Type: GrantFiled: June 5, 2007Date of Patent: June 30, 2009Assignee: DENSO CORPORATIONInventors: Shoichi Yamauchi, Yoshiyuki Hattori, Kyoko Okada
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Patent number: 7544571Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.Type: GrantFiled: September 28, 2006Date of Patent: June 9, 2009Assignee: Fairchild Semiconductor CorporationInventor: Chanho Park
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Patent number: 7537995Abstract: A method for fabricating a dual poly gate in a semiconductor device is disclosed.Type: GrantFiled: June 8, 2007Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Byung Soo Eun, Hyun Seok Kang
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Patent number: 7537994Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.Type: GrantFiled: August 28, 2006Date of Patent: May 26, 2009Assignee: Micron Technology, Inc.Inventors: Ted Taylor, Xiawan Yang
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Patent number: 7518184Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.Type: GrantFiled: June 26, 2006Date of Patent: April 14, 2009Assignee: Micron Technology, Inc.Inventor: Luan C. Tran
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Patent number: 7507631Abstract: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.Type: GrantFiled: July 6, 2006Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Brian Joseph Greene, Judson Robert Holt
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Patent number: 7504306Abstract: A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.Type: GrantFiled: April 4, 2006Date of Patent: March 17, 2009Assignee: Fairchild Semiconductor CorporationInventors: Steven Sapp, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
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Patent number: 7501323Abstract: A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.Type: GrantFiled: April 12, 2005Date of Patent: March 10, 2009Assignee: Fairchild Semiconductor CorporationInventor: Jun Zeng
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Patent number: 7485532Abstract: A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.Type: GrantFiled: March 20, 2008Date of Patent: February 3, 2009Assignee: Fairchild Semiconductor CorporationInventors: Bruce D. Marchant, Ashok Challa
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Patent number: 7465622Abstract: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.Type: GrantFiled: September 29, 2006Date of Patent: December 16, 2008Assignee: Nanya Technology Corp.Inventor: Shian-Jyh Lin
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Patent number: 7459744Abstract: A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion of a floor of the first trench. The charge storage stack includes a layer of discontinuous storage elements (DSEs). Electrically conductive spacers formed on opposing sidewalls of the first trench adjacent to respective charge storage stacks serve as control gates for the device. The DSEs may be silicon, polysilicon, metal, silicon nitride, or metal nitride nanocrystals or nanoclusters. The storage stack includes a top dielectric of CVD silicon oxide overlying the nanocrystals overlying a bottom dielectric of thermally formed silicon dioxide. The device includes first and second injection regions in the layer of DSEs proximal to the first and second diffusion regions.Type: GrantFiled: September 22, 2006Date of Patent: December 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Cheong M. Hong, Chi-Nan Li
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Patent number: 7449401Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.Type: GrantFiled: December 29, 2005Date of Patent: November 11, 2008Assignee: Hynix Semiconductor Inc.Inventors: Tae-Woo Jung, Sang-Won Oh
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Patent number: 7423317Abstract: A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.Type: GrantFiled: July 24, 2006Date of Patent: September 9, 2008Assignee: International Rectifier CorporationInventors: Hugo R. G. Burke, David Paul Jones, Ling Ma, Robert Montgomery
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Patent number: 7378312Abstract: An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.Type: GrantFiled: December 8, 2006Date of Patent: May 27, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Ji-Young Kim
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Patent number: 7354827Abstract: According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.Type: GrantFiled: April 6, 2005Date of Patent: April 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-Won Seo, Du-Heon Song, Sun-Joon Kim, Jin-Woo Lee
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Patent number: 7332397Abstract: A method for fabricating a semiconductor device includes forming a doped polysilicon layer on a semiconductor substrate forming an oxide film for device isolation in a predetermined region of the doped polysilicon layer and the semiconductor substrate, forming an etch stop layer on the oxide film for device isolation and the doped polysilicon layer, etching a predetermined region of the etch stop layer, the doped polysilicon layer and the semiconductor substrate to form a trench defining a gate region, depositing a gate oxide film on the gate region, forming a gate electrode layer and a hard mask layer filling the trench, and polishing the gate electrode layer and the hard mask layer to expose the etch stop layer and to form a gate in the gate region.Type: GrantFiled: June 10, 2005Date of Patent: February 19, 2008Assignee: Hynix Semiconductor Inc.Inventor: Sang Cheol Kim
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Patent number: 7268043Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.Type: GrantFiled: November 30, 2006Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Nak-Jin Son, Ji-Young Kim
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Patent number: 7265024Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.Type: GrantFiled: January 10, 2006Date of Patent: September 4, 2007Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng