Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.

Abstract: Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.

Abstract: A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

Abstract: A transistor structure and method to fabricate same, the semiconductor transistor structure comprising a transistor having an effective channel width that is greater than a lateral surface dimension spanned by an overlying transistor gate. A method of forming a transistor structure during semiconductor fabrication comprising the steps of forming at least one recessed region into a semiconductive material defined as an active area for the transistor; forming a transistor gate dielectric material directly and substantially comformally on the semiconductive material and into the at least one recessed region; and forming a transistor gate electrode substantially comformally overlying the transistor gate dielectric material and extending into the at least one recessed region such that the transistor gate electrode spans a width of the active area.

Abstract: The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.

Abstract: The present invention provides an on-chip temperature sensor formed of an MOS tunneling diode. The temperature sensor is formed by processes which are compatible with the below 0.13 &mgr;m CMOS technology, so it can be fabricated with MOS devices and integrated into an IC chip. Since the MOS tunneling diode has the characteristic of a diode, a formula showing the exponential relationship between the gate current and the substrate temperature can be obtained when the MOS tunneling diode is biased inversely at a constant voltage. After the current of the MOS tunneling diode is detected, the substrate temperature which represents the real temperature of the IC chip can be figured out.

Abstract: Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate, forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

Abstract: A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Abstract: An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Abstract: A power semiconductor device having a trench gate structure in which it is possible to reduce the number of required masks and to improve its characteristics, and a method for manufacturing the same, includes a semiconductor substrate and a semiconductor region of a first conductive type formed on the semiconductor substrate. A source region of a second conductive type is formed on the semiconductor region. A trench is formed to pass through the source region and the semiconductor region of the first conductive layer. A first conductive layer formed to be insulated from the semiconductor substrate by interposing a gate insulating film, and a gate formed of a second conductive layer surrounded by the first conductive layer are formed in the trench. An interlayer dielectric film is formed on the semiconductor substrate. A gate electrode is formed connected to the gate through a contact hole formed in the interlayer dielectric film.

Abstract: A semiconductor device is formed such that a contact surface between a p-type high-concentration semiconductor region and an n-type high-concentration buffer region assumes a convexo-concave shape. This makes it possible to enlarge an area of the contact surface between the p-type high-concentration semiconductor region and the n-type high-concentration buffer region. As a result, holes are injected into an n-type low-concentration drift region from the p-type high-concentration semiconductor region with higher efficiency and with a less voltage drop between the pn-junction. Thus, effects of conductivity modulation can be achieved sufficiently and the on-resistance and the voltage drop of an IGBT can be lowered.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n−-type diffusion region.

Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Abstract: Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: A method of manufacturing a semiconductor component includes disposing a layer (120) of an electrically insulative material over a semiconductor substrate (110), etching a trench (310) into the layer and the semiconductor substrate, disposing a layer (410) of a semiconductor material in the trench, and forming a gate contact (1410) in the trench.

Abstract: An insulating gate type semiconductor device has a plurality of trench gate electrodes provided substantially in parallel. In this semiconductor device, among the trench gate electrodes, a thinning-out trench gate electrode excluding a channel-forming trench gate electrode is insulated from a gate wire and is connected to an emitter electrode or to a predetermined electric potential generating device for generating a negative electric potential with respect to an emitter potential. With this construction, a gate capacitance is decreased without drawbacks such as a decline of manufacturing yield and an increase in gate wire resistance, there are decreased oscillations of waveforms of voltage and current when in switching in the case of an element having a large area and operating the elements in parallel.

Abstract: Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.

Abstract: A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement. Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms.

Abstract: A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

Abstract: A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.

Abstract: A transistor (30) uses a single continuous base region (40) with an undulating structure. The semiconductor device is an insulated gate field effect transistor having a semiconductor substrate with a plurality of doped base branches, which extend into the semiconductor substrate, form into a single base region for the entire transistor. Each of the plurality of base branches (82) is undulating and of substantially constant width, and each of the base branches undulates in-phase with the immediately adjacent base branches. A continuous gate layer (34) overlies the semiconductor substrate and is self-aligned to the plurality of base branches. The undulating structure of the base region improves channel density, and thus lowers on-resistance, and the use of a single base region ensures that all portions of the base region throughout the device will be at a substantially constant electric potential.

Abstract: The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.

Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Abstract: A transistor structure has a recess formed in the upper surface of its base layer, an epitaxial (epi) layer grown on the upper surface in a manner to create a surface depression in the outer surface of the epi layer, the surface depression being generally aligned with the recess. A semiconductor element, such as a well or a gate, is formed on the epi layer aligned with the recess.

Abstract: A method for fabricating high voltage semiconductor devices having a gradient doping of a drift region which comprises N-well 1 and N-well 2 with two different doping densities. This method results in the lift in device's current drive capability and as well as its breakdown voltage. The method further comprises forming a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, the extension in channel length and the placement of both the channel and drift regions change to vertical direction, all of those result in a greater reduction in the occupied chip area. These advantages attribute to the formation of a buried gate electrode by trench etching method.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer of an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: An electronic field reduction in a corner of a trench section of a semiconductor is achieved by forming a p-type base region in a source area of an n-type drain region, and both an n-type source region and a gate leading region are formed in a surface area of the p-type base region separately from each other. A trench section is formed in both the source region and gate leading region to reach the drain region. Polysilicon is formed in the trench section and on the surface of a semiconductor substrate with a gate insulation film interposed therebetween and then thermally treated. An interlayer insulation film is deposited on the entire surface of the semiconductor substrate, and then contact holes reaching the gate leading region and the source and base regions in the peripheral portion of the trench section in the source region are formed. A source/base electrode which contacts both the source and base regions through one of the contact holes is formed.

Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type.

Abstract: A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage.

Abstract: A method for fabricating a high-bias semiconductor device contains several steps. A first-type semiconductor substrate is provided. A well doped with a second-type dopant is formed. Two episodes of ion implantation are performed to form two drift regions. The lower drift region has lighter dopant density but a greater thickness than the upper drift region. An annealing process is performed on the drift regions. A first pad oxide layer is formed over the drift regions. A first silicon nitride layer is formed over the first pad oxide layer. A trench is formed in the well. The first silicon nitride layer and the first pad oxide layer are removed. A second pad oxide layer is formed over the substrate including the trench bottom surface. A second silicon nitride layer is formed over the substrate on the second pad oxide layer other than the sidewall surface of the trench. A field oxide layer is vertically formed on each sidewall of the trench. The second silicon nitride layer is removed.

Abstract: A field effect transistor (FET) with a V-shaped trench gate in a semiconductor substrate having gate oxide on the walls of the trench and a gate electrode material within the trench walls, and source/drain impurities in the semiconductor substrate and abutting the gate oxide. The resultant FET structure comprises a non-self align V-shaped gate with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Because of the V-shaped structure of the gate, the effective length of the channel only extends from the edge of the source to the tip of the V-shaped gate. Due to this characteristic, the width of the gate at the surface of the semiconductor substrate can be two or more time the distance of the desired channel length thereby permitting conventional lithography to be used to fabricate gate lengths much shorter than the lithography limit. Preferably, the bottom or tip of the V shaped gate is rounded and concave.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Abstract: A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantation of dopant into trench sidewalls creates channel regions oriented at an angle relative to the horizontal bit lines. Disposing successive diffused bit lines in vertically separated planes enables fabrication of ROM cells having full channel lengths which occupy a smaller surface area. Tilted ion implantation may be utilized to introduce dopant into channel regions.

Abstract: On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on the inner surface of the groove by wet oxidation and, further, this oxide film is removed by wet etching, after which the surface of the semiconductor substrate located on the outer-peripheral side of the groove from an angular portion defined between a side surface of the groove and the surface of the semiconductor substrate is exposed. Then, the inner surface of the groove and the exposed surface of the semiconductor substrate are oxidized to thereby form a LOCOS oxide film, and thereafter this LOCOS oxide film is removed. As a result of this, the angular portion is made round, thereby enabling the avoidance of the concentration of an electric field on the angular portion of the groove.

Abstract: The present invention is a layered structures of substantially-crystalline semiconductor materials and processes for making such structures. More particularly, the invention epitaxial grows a substantially-crystalline layer of a second elemental semiconductor material on a substantially-crystalline first semiconductor material different from the second material in which there is a significant mismatch in at least one dimension between the crystal-lattice structures of the two materials.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased.

Abstract: The semiconductor device includes (A) a first MOS transistor including (a) a main surface at a part of which recesses are formed, an inner surface of the recesses defining a crystal plane being able to be thermally oxidized at higher speed than the main surface, and (b) an insulator formed on the inner surface of the recesses, the inner surface of the recesses working as a channel region and the insulator working as a gate insulator in the first MOS transistor, and (B) a second MOS transistor in which the main surface works as a channel region and an insulator formed on the main surface works as a gate insulator, the gate insulator of the first MOS transistor having a greater thickness than that of the gate insulator of the second MOS transistor. Thus, above the thinner gate insulator is formed the second MOS transistor, while above the thicker gate insulator is formed the first MOS transistor having a higher breakdown voltage than that of the second MOS transistor.