Abstract: The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer.

Abstract: A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening.

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

Abstract: A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; and a first lightly-doped source or drain (LDD) region and a first pocket region adjacent to the first gate electrode. The logic MOS device includes a second gate electrode on the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region and a second pocket region adjacent the second gate electrode, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than a impurity concentration of the respective second LDD region and the second pocket region.

Abstract: A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack has four components: a first dielectric layer disposed over the substrate; a charge accumulation layer capable of holding charge in a portion thereof to store information and disposed over the first dielectric layer; a second dielectric layer disposed over the charge accumulation layer; and a control gate disposed over the second dielectric layer. The select stack has two components: a third dielectric layer disposed over the substrate and a select gate, capable of inverting an underneath channel region to function as a source or a drain of the memory cell, disposed over the third dielectric layer.

Abstract: A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.

Abstract: A method for fabricating a semiconductor device is provided. A first active region and a second active region are defined in a substrate. An electrode covering the first active region and the second active region is formed on the substrate. A first sacrificial layer is formed on the second active layer. A first work function electrode is formed on the first active layer by performing a first doping process to a portion of the electrode. The first sacrificial layer is removed. A second sacrificial layer is formed on the first active layer.

Abstract: One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.

Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

Abstract: A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.

Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: A method for forming a semiconductor device is disclosed. A substrate comprising trenches are provided. Dopants are doped into a region of the substrate neighboring a sidewall of the trenches by using an isotropic doping method. A gate dielectric layer is formed on the sidewall of the substrate. A gate electrode is formed in the trenches, wherein the gate electrode protrudes a surface of the substrate.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate having a plurality of isolation areas formed therein, the isolation areas defining an active region, a gate electrode formed on the active region, spacers formed on sides of the gate electrode, a source region formed in the substrate at a side of the spacer formed at a first side of the gate electrode, a drain region formed in the substrate at a side of the spacer formed on a second side of the gate electrode, and lightly doped drain regions formed in the substrate below the spacer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.

Abstract: The method for manufacturing a semiconductor device according to the invention includes the first doping step of doping source/drain regions including source/drain extension regions adjacent to a channel region of a MOS transistor, the second doping step of doping pocket implant regions disposed from the bottom of the source/drain extension regions in the depth direction, the step of forming an amorphous surface layer at the surface of a semiconductor crystal substrate so as to overlap the source/drain extension regions and the pocket implant regions, and the recrystallization step of recrystallizing the amorphous surface layer by a solid-phase epitaxy technique.

Abstract: A highly integrated semiconductor device has a device isolation layer demarcating a first active region in a first region of a substrate, and a second active region in a second region of the substrate. A first gate pattern and a second gate pattern are formed on the first active region and the second active region, respectively. A first spacer layer and a second spacer layer are formed over the gate patterns. Then, the second and first spacer layers in the first region are anisotropically etched to form a gate spacer on sidewalls of the first gate pattern. The gate spacer has a lower spacer section formed from the first spacer layer and an upper spacer section formed from the second spacer layer. Then, ions are implanted into the first active region. Subsequently, the upper spacer section and the second spacer layer on the first and second regions, respectively, are removed.

Abstract: A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can provide a trench MOS transistor having an up-drain structure. The semiconductor device can include a first conductive type well in a semiconductor substrate, a second conductive type well on the first conductive type well, trenches formed by removing portions of the second conductive type well and the first conductive type well; gates provided in the trenches with a gate dielectric being between each gate and the walls of the trench, a first conductive type source region and a second conductive type body region on the second conductive type well, the first conductive type source region surrounding a lateral surface of the gate, and a common drain between the gates, the common drain being connected to the first conductive type well.

Abstract: A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.

Abstract: In order to provide a semiconductor apparatus and a production method of the semiconductor apparatus that achieves a small interface trap density by implantation of fluorine and that achieves both small property fluctuation and a small leak current, a semiconductor apparatus includes: a semiconductor substrate; a well layer formed on the semiconductor substrate; a channel dope layer formed on the well layer; a source/drain diffused layer provided at an upper peripheral of the channel dope layer; gate electrodes formed on the channel dope layer via a gate insulation film; a polycrystalline silicon plug which is formed between the gate electrodes and which touches the source/drain diffused layer while piercing the gate insulation film; and fluorine which is selectively implanted only in a source area of the source/drain diffused layer.

Abstract: A device includes a semiconductor layer on an insulating layer; a gate insulator on the semiconductor layer; a comb-shaped gate electrode on the gate insulator, including a base portion extending in a first direction and tooth portions extending in a second direction from one side surface of the base portion; a comb-shaped low-concentration diffusion layer in the semiconductor layer under the gate electrode having a first electroconductive type; a source layer in the semiconductor layer on the tooth portion side of the base portion having second electroconductive type with high concentration; a drain layer in the semiconductor layer on a side of the base portion opposite the tooth portion side having second electroconductive type with high concentration; and an extraction layer in the semiconductor layer between the source and the device isolating layers having first electroconductive type with high concentration, and connected with the diffusion layer.

Abstract: A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate electrode is formed over the semiconductor substrate in the first region. A first photoresist film covering the second region and having an opening exposing the first active region and having an edge on the border portion of the opening positioned nearer the second active region than a middle of the device isolation film is formed over the semiconductor substrate with the gate electrode. Impurity ions are implanted from a direction tilted from a normal direction of the semiconductor substrate with the first photoresist film and the gate electrode as a mask to form pocket regions in the semiconductor substrate on both sides of the gate electrodes.

Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.

Abstract: A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; and a first lightly-doped source or drain (LDD) region and a first pocket region adjacent to the first gate electrode. The logic MOS device includes a second gate electrode on the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region and a second pocket region adjacent the second gate electrode, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than a impurity concentration of the respective second LDD region and the second pocket region.

Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.

Abstract: A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set so that the implanted ions may not break through the polysilicon gate.

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The rate electrodes of tantalum can withstand this heat treatment.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

Abstract: According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.

Abstract: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.

Abstract: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Abstract: Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. A PSG (HDP-PSG: Phospho Silicate Glass) film containing a conductive impurity is formed as an interlayer insulating film for burying the gate electrode structures at film-formation temperature of 650° C. or lower by a high-density plasma CVD (HDP-CVD) method.

Abstract: A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in the semiconductor substrate. Thus, the gate insulation layer is formed before forming the buried impurity region, thereby substantially reducing impurity diffusion that can be caused by a thermal process for forming the gate insulation layer. In addition, the gate insulation layer is not exposed, thus protecting the gate insulation layer from being recessed.

Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

Abstract: A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

Abstract: To increase the density of memory cells, a multibit memory cell (10, 50, 80, 110) can be manufactured by preventing the formation of at least one of the extension regions usually formed for the source or drain region. In one embodiment, a single mask (24) blocks the doping of the extension regions during ion implantation. If a tilt implantation process is used to form desired extension regions, two masks may be used. The process can also be integrated into a disposable spacer process. By blocking the extension region for a current electrode, a programmable region (32, 76, 102, 132) is formed adjacent a current electrode. The programmable region enables a two-bit memory cell to be formed.