Abstract: After completion of wiring strips on an inter-level insulating structure, a field effect transistor is checked to see whether or not the threshold voltage falls within a design range, if the threshold voltage is out of the design range, hydrogen ion is implanted through the inter-level insulating structure, the gate electrode and the gate insulating layer into the channel region of the field effect transistor, and the resultant semiconductor structure is annealed at 400 degrees in centigrade for 20 minutes so as to partially deactivate the dopant impurity in the channel region.

Abstract: This invention provides contact programmable ROM which shortens TAT. The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor substrate, the first interlayer insulating layer 20 is formed on the whole surface, the first opening 21 is formed on the first interlayer insulating layer 20 above one source/drain region 15A of each memory cell, metal interconnect material 22 is filled in the first opening 21 to from a contact hole, and the second interlayer insulating layer 23 is formed over the metal interconnect material 22 and first interlayer insulating layer 20, and (b) a step in which the second opening 24 is formed on the second interlayer insulating layer 23 above the contact hole of specified memory cells, and interconnecting layer 25 is connected electrically to the contact hole is formed over the second interlayer insulating layer 23.

Abstract: A method is provided to fabricate a mask ROM device via a medium current implanter. For fabricating the mask ROM device, first, formation of an array of MOS transistors on a semiconductor substrate is achieved. Each of the MOS transistors includes a gate oxide film, a gate electrode, a source region and a drain region. After the formation of the array of transistors, a USG layer, a BPSG layer, metal electrodes and a passivation layer are sequentially formed. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the BPSG layer within the openings are successively etched until the remained BPSG layer is in a predetermined thickness. Finally, ROM code ions are implanted into the substrate via a medium current implanter through the openings.

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.

Abstract: Improved methods for forming integrated circuit devices with alignment structures such as a read-only memory (ROM) array in preparation for code programming with a mask is disclosed. In one embodiment, a gate oxide layer is deposited over a substrate and a gate stack layer is formed over the gate oxide layer. The gate stack layer includes a conductive layer and a sacrificial gate layer formed above the conductive layer with a thin layer of etch stop material in between. The gate stack layer is patterned and etched to form a plurality of wordlines having openings therebetween. An ion barrier layer is deposited over the patterned gate stacks, filling the openings. The ion barrier layer is then etched back to form alignment structures in the openings. A code programming mask, is deposited over the resulting structure and patterned to expose portions of the sacrificial gates. The exposed portions of the plurality of sacrificial gates are removed, followed by ion implantation in the designated channel regions.

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines.

Abstract: A metal code process for a read-only memory (ROM) combines the alignment dip back process (to reduce the polyoxide thickness over the gate electrode and to protect the field oxide) with a double charge implant approach to provide the function of a depletion mode ROM cell. The alignment dip back process also avoids leakage current problems. A stable depletion mode device character is achieved by implant step energies greater than 150 keV.

Abstract: A method for forming a Trench Mask ROM cell comprises the steps of: Providing a substrate doped lightly with p-type dopant; forming plural trenches and then, forming a gate layer on each trench, further, implanting n+-type ions on substrate beneath the gate oxide layer on bottom of each trench and position between each two adjacent trench; and then, forming a nitride layer on the gate oxide layer; forming an oxide layer on the nitride layer and each trench being filled with the oxide layer; and removing the oxide layer and the nitride layer of partial trenches, namely, partial trenches reserving the oxide and the nitride layer to define coding regions of the Trench Mask ROM cell; finally, depositing a polysilicon layer on the top surfaces of the substrate wherein the polysilicon being word line of the Trench Mask ROM cell.

Abstract: A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device by carrying out a second impurity first-code selective ion-implantation, into at least a first-selected one of said plurality of cell regions doped with a first impurity to have a first threshold voltage level so that the at least the first-selected one of said cell regions has a second threshold voltage level which is different from the first threshold voltage level, the second impurity of the first-code selective ion-implantation being heavier than said first impurity so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of the cell regions.

Abstract: A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then removed and a neutral ion species such as Silicon or Germanium is implanted between the source and drain regions in the region that is to become the doped channel region. A dopant substance is next implanted into the channel region, which is then exposed to ultra-rapid thermal annealing to cause the dopant to form a box-like, super-steep retrograded channel profile. The gate is then re-formed over the now activated doped channel region.

Abstract: A method of fabricating high density multiple states mask ROM cells on a semiconductor substrate is disclosed. The method comprises the following steps. Firstly, the array of buried bit line is formed on semiconductor substrate. Then, a CVD oxide film is deposited on said substrate. The first coding mask is applied to dip out the CVD oxide film on the uncoded regions. Then, a thin gate oxide film is thermally grown on said substrate. At the same time, the CVD oxide film is densified and the N+source/drain junction of buried bit lines is formed. A conductive layer is then deposited on all area followed by defining the word lines. The second coding process is performed by using a high energy boron ion implantation through the conductive layer and gate oxide film into said predetermined regions. By combination of the first CVD oxide coding process and the second boron ion implantation coding process, a high density mask ROM with a multiple states is fabricated.

Abstract: A method of fabricating mask ROMs combines the code mask and via mask into a combination mask such that the isolation layers are removed to reveal the memory cells to be coded and the metal layers to be electrically contacted simultaneously, and the bury implantation process can be shifted and combined with the back-end process. Consequently, the delivery of mask ROM finished-products can be speeded, and the fabricating cost reduced.

Abstract: Sewage water containing phosphate is passed through an anaerobic treatment chamber containing reductive-iron-dissolution (RID) material, such as ferric oxyhydroxide solids. The RID material releases ferrous ions into solution, which combine with the phosphate to produce ferrous-phosphate minerals, such as vivianite, which precipitate in the anaerobic chamber. Also, iron and phosphate remaining in the water can precipitate as ferric-phosphate minerals such as strengite, when the water is later aerated.

Abstract: A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, thereby forming a contact window. The code implantation is subsequently carried out so these ions can easily reach the coding positions via the contact opening.

Abstract: A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer.

Abstract: A method is provided for manufacturing a memory cell with a increased threshold voltage accuracy. The memory cell has a substrate including a plurality of first conducting lines in a first direction and a plurality of second conducting lines in a second direction. The method includes the steps of forming a photoresist layer over the first and the second conducting lines, forming a window on the photoresist layer to expose a portion of the second conducting lines, thinning the portion of the second conducting lines in the windows, and doping impurities into the substrate between two of the first conducting lines to form the memory cell.

Abstract: A method of fabricating a one-time programmable read only memory (OTP-ROM) with reduced size is disclosed. In accordance with the method of the present invention, a stacked structure is formed on a substrate. The stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate. The substrate beside the stacked structure is exposed by the stacked structure. An implanted region is formed in the exposed substrate beside the stacked structure. A spacer is formed on a sidewall of the stacked structure. A silicide layer is formed on the implanted region. A silicon nitride layer is formed to cover the second oxide layer, the spacer, and the silicide layer. A second polysilicon layer is formed to cover the silicon nitride layer. The second polysilicon layer is patterned to form a control gate. The first polysilicon layer is further patterned to form a floating gate.

Abstract: A method is provided to fabricate a mask ROM device via a medium current implanter. For fabricating the mask ROM device, first, formation of an array of MOS transistors on a semiconductor substrate is achieved. Each of the MOS transistors includes a gate oxide film, a gate electrode, a source region and a drain region. After the formation of the array of transistors, a USG layer, a BPSG layer, metal electrodes and a passivation layer are sequentially formed. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the BPSG layer within the openings are successively etched until the remained BPSG layer is in a predetermined thickness. Finally, ROM code ions are implanted into the substrate via a medium current implanter through the openings.

Abstract: A method for fabricating a multi-level mask ROM includes the steps of forming a plurality of memory cell transistors, depositing and planarizing a dielectric film covering the memory cell transistors, forming an opening in the dielectric film in the area for a selected memory cell transistor, and injecting impurity ions through the opening and the gate electrode of the selected memory cell transistor into the channel area thereof to obtain a desired threshold voltage. Planarization of the dielectric film reduces scattering of the injected ions, thereby preventing transverse extension of the injected ions and achieving a higher integration of the multi-level mask ROM.

Abstract: A semiconductor nonvolatile storage that is an inter-gate insulating film breakdown type memory is configured by providing a field oxide film on a semiconductor substrate 1, a gate electrode on the field oxide film and a mask oxide film on the surface of the gate electrode, forming an opening m the mask oxide film and forming a memory oxide film on the gate electrode exposed thereat, providing a memory gate electrode of a size extending from over the memory oxide film to over the mask oxide film, and making the thickness of the memory oxide film thinner than the thickness of the mask oxide film.

Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time of the read operation to the memory cells. The binary data stored in each memory cell is dependent on whether one contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value.

Abstract: A method for forming mask read-only memories comprises: A gate oxide layer is formed on a semiconductor substrate. A polysilicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on said polysilicon layer. The gate structures are defined by patterning the silicon nitride layer and the polysilicon layer. Subsequently, the silicon oxide spacers are formed on the sidewalls of the gate structures. An ion implantation is performed to form the buried bit lines in said semiconductor substrate between said gate structures. A BPSG layer is formed on said semiconductor substrate. Then, the BPSG layer is polished until the top surface of said gate structures and the silicon nitride layer is removed. A conductive layer is formed along the surfaces of said residual BPSG layer, silicon oxide spacers and polysilicon layer.

Abstract: A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region.

Abstract: A method of manufacturing a semiconductor device for preventing ESD damage is disclosed. A semiconductor device for preventing against ESD damage according to a first embodiment of the present invention, is fabricated as follows. Firstly, first impurity ions of a first conductivity type are implanted into a first region of a substrate of a semiconductor device using a first ion implantation, to form a first impurity ion layer. Here, a junction region will be formed in the first region and is connected to an input pad. Second impurity ions of the first conductivity type are then implanted into a second region of the substrate using a second ion implantation, to form a second impurity ion layer over the first ion impurity ion layer. Here, the second region includes the first region. Next, third impurity ions of a second conductivity type are implanted into the substrate of both sides of the first and second impurity ion layers, using a third ion implantation, to form a third impurity ion layer.

Abstract: A method to fabricate double poly gate high-density multi-state flat mask ROM cells on a silcon substrate is disclosed. The method comprises the following steps. Firstly, an in-situ n+ first polysilicon/pad oxide layer is deposited on the silicon substrate, and then an ARC layer such as nitride layer is deposited to improve the resolution during the lithography process for pateterning a first formed word line. After forming a plurality of dual nitride spacers on sidewalls of the first patterned gate, a first photoresist coating on all resultant surfaces except the two predetermined regins, a first boron or BF.sub.2.sup.+ coding implant into the silicon substrate is carried out. The photoresist is then stripped and an oxidaiton process conducted in O.sub.2 ambient to grow oxide layers on all surfaces of the silicon substrate using the nitride layer as a hard mask.

Abstract: The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a forth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.

Abstract: A method for fabricating a mask read only memory (ROM) is provided. A plurality of word lines functioning as a gate electrode of a cell transistor and a plurality of first anti-reflective layer patterns are sequentially formed on a semiconductor substrate. An insulator layer is formed over the entire surface of the semiconductor substrate where the plurality of first anti-reflective layer patterns and the plurality of word lines are formed. A spacer is formed at the side walls of the respective word lines by anisotropically etching the insulator layer until the plurality of word lines are exposed. A second anti-reflective layer is formed over the entire surface of the semiconductor substrate where the spacer is formed. A photoresist pattern opening the upper portion of a predetermined region of at least one word line selected among the plurality of word lines of the cell transistor to be programmed is formed on the second anti-reflective layer.

Abstract: The invention relates to a method of automatically shifting from the fabrication of an EPROM cell to the fabrication of a ROM cell, which method is specifically intended for semiconductor electronic circuits having a resident memory and is of the type wherein the structure of at least one memory cell transistor is defined on a semiconductor substrate using photolithographic techniques including an active area and a channel region, the cell being adapted to acquire a logic state selected by the user. Advantageously, the conductivity of the active area is changed to suit the logical contents that the cell is intended to contain.

Abstract: A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.

Abstract: A method of manufacture for a multiple stage ROM unit capable of coding the multiple stages with a single coding implantation and a method of manufacturing the same.The ROM includes a semiconductor substrate covered by an insulating layer. A gate structure is provided above the insulating layer. A channel region is located on the substrate beneath the gate structure. Source/drain regions are disposed on the semiconductor substrate on each side of the channel region. A cap partially covers the top of the gate structure so as to divide the channel region therebelow into a first channel region and a second channel region such that multiple-level threshold voltages may be coded in the ROM.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

Abstract: A method of making an IGFET with a selectively doped channel region is disclosed. The method includes providing a semiconductor substrate with a device region, forming a gate over the device region, forming a masking layer that partially covers the gate and the device region, implanting a dopant into portions of the gate and the device region outside the gate that are not covered by the masking layer, transferring the dopant through the uncovered portion of the gate into a portion of an underlying channel region in the device region, thereby providing the channel region with a non-uniform lateral doping profile and adjusting a threshold voltage, and forming a source and a drain in the device region. The dopant can be implanted through the portion of the gate into the portion of the channel region, or alternatively, the dopant can be diffused from the portion of the gate into the portion of the channel region.

Abstract: A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.

Abstract: The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.

Abstract: A technique for storing multiple bits per cell in a read only memory device, provides for two kinds of code implants in the memory array. A shallow implant such as used in prior art mask ROMs is used for coding a first bit, and a deeper implant is used for coding a second bit in the memory cells. Furthermore, the cells are implemented in a semiconductor substrate so that the channels of the transistors in the mask ROM can be biased. The memory cells include as isolation layer formed in the semiconductor substrate, and a channel well formed in the isolation layer. The device includes resources to apply a first bias potential such as ground, to channel regions of memory cells in the array. When the first bias potential is applied through the channel regions, the memory cells have particular thresholds determined at least in part by the dope concentrations in the channel regions. The device also includes resources to apply a second bias potential to the channel regions of the memory cells.

Abstract: An improved process of fabricating a read only memory device (ROM's) wherein the buried N+ lines have desirable very narrow widths and are closely spaced. The process provides that masking stripes are formed with vertical sidewalls and that spacers are formed on the sidewalls. The areas between the spacers are filled in. The spacers are etched away to form narrow closely spaced openings. Ions are implanted through the openings to form closely spaced buried lines.

Abstract: A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantation of dopant into trench sidewalls creates channel regions oriented at an angle relative to the horizontal bit lines. Disposing successive diffused bit lines in vertically separated planes enables fabrication of ROM cells having full channel lengths which occupy a smaller surface area. Tilted ion implantation may be utilized to introduce dopant into channel regions.

Abstract: Disclosed is a method of fabricating memory devices. By the method, a silicon nitride layer is used as a mask to form oxide layers on the lateral sides of the word lines through high-temperature heat treatment as source/drain annealing or oxidation. An etching process is subsequently used to remove the silicon nitride layer so as to expose the polysilicon layer on the word lines. After that, metal, preferably aluminum, is selectively grown the exposed polysilicon layer, which allows the resistance of the word lines to be significantly lowered thereby increasing access speed of the memory device.

Abstract: A process for ROM coding is described. First, the active device areas and isolation regions are defined on a semiconductor substrate. Then, silicon isotopes (Si.sup.30) are implanted into the active device areas to form isotope regions. Next, the remaining portions of the MOSFET structures are then formed. Next, an interlayer dielectric layer, and a metal layer are sequentially deposited and patterned to finish the basic ROM structure. Upon the receipt of an order, a passivation layer is deposited overlaying the interlayer dielectric layer. Next, a photoresist layer is coated over the passivation layer, and code implant windows are patterned. Finally, neutron irradiation is performed to activate the silicon isotopes into N-type phosphorus ions.

Abstract: In a conventional method, formation of an intermediate layer to serve as an insulating layer between a metal terminal on the surface of the device and a gate electrode of the device, along with heat treatment of the intermediate layer, is executed after formation of implanted diffusion layers to serve as bit lines of the device. In the method for manufacturing semiconductor memory devices according to the present invention, formation of the intermediate layer and heat treatment thereof are executed before formation of the implanted diffusion layers. The formation of the implanted diffusion layers is executed by introducing an impurity material into a memory cell region of the device with an energy enough to penetrate the intermediate layer. According to the method, heat diffusion of the impurity material due to the heat treatment step is prevented, and thus `Lmin`, i.e. the minimun channel length, can be set shorter and higher degree of integration of devices is made possible.

Abstract: A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer.

Abstract: A method is provided for fabricating a ROM device for permanent storage of multi-level coded data therein. By the method, an array of MOSFET-based memory cells are first formed on a substrate, each being formed with an island-like gate region and a pair of source/drain regions. In accordance with customer specification, different groups of the memory cells are specified to respectively store a first, a second, a third, and a fourth value of the multi-level coded data. In the mask programming process, a first code-implantation process is performed to implant impurities into the respective channel regions of the second and fourth selected groups of the memory cells so as to vary the threshold voltage thereof. Then, an insulating layer is formed over the wafer, covering all of the memory cells. Next, a second code-implantation process is performed to form a plurality of contact windows in the insulating layer directly above the island-like gates of the first and second selected groups of the memory cells.

Abstract: A method of making a read only memory device includes forming a gate oxide layer and a silicon nitride layer in sequence above a silicon substrate. The gate oxide layer and the silicon nitride layer are etched to define a plurality of parallel strips extending in a first direction. Ions are implanted, using the parallel strips as masks, into the silicon substrate to form a plurality of buried bit lines extending in the first direction. A sidewall spacer is formed on respective sidewalls of the parallel strips. A silicide layer is formed over an exposed surface of the respective bit lines. An insulating layer is formed to cover any exposed surfaces, and fill a space located between adjacent parallel strips and above the bit lines. A portion of the insulating layer is removed to expose the silicon nitride layer and form a planar surface. The silicon nitride layer is patterned to form a plurality of coding areas. A polysilicon layer is formed to cover the coding areas as well as any other exposed surfaces.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A ROM structure and its method of manufacture using separate parallel trench bit lines for increasing memory component density as well as using a diode as the fundamental memory unit, each diode having a junction formed inside a bit line with a forward biased voltage of about 0.4 V and a reverse biased voltage dependent upon the doping condition in an N.sup.- region. At a junction between a word line and a bit line, either an ON state or an OFF state diode memory unit is created depending on whether a contact opening in the insulating layer for connection between the two is formed or not. When a definite operating voltage is applied to the word line, the stored information bit in the diode memory unit can be read off from the bit line by sensing a cut-off or a conducting current representing previous program coding of the diode memory unit.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

Abstract: A fabricating method for a ROM device uses the Shockly diode as a memory cell in the ROM device. In the present invention, the current of the memory cell is larger than that of a convention one. In the conventional ROM device, the code is programmed by making use of the channel transistor as the memory cell and implanting. In the present invention, the code is programmed by defining contact windows of the ROM device to prevent the ROM device from the shortcomings of limited current. In addition, the memory cells of the ROM device of a Shockly diode are isolated by an insulating layer, resulting in a smaller area for the device and improved integrity.

Abstract: A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.