Abstract: A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.

Abstract: A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of, programming the same are disclosed. Furthermore, a method of single bit erasing combined with block erasing of a plurality of cells of two or more is disclosed through the application of a negative voltage forced onto the control gate of the selected cell. Thus, by providing the single bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.

Abstract: A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is formed on an upper surface of the gate electrode and on an upper surface of a substrate on which source and drain regions are formed, thereby providing a contact hole self-aligned between the gate electrodes. Also, an ion implantation process is performed on the entire active region after the contact hole is filled with metal such as tungsten, and an impurity region is formed only on a lower portion of the gate electrode.

Abstract: A process for fabricating a VDMOS power transistor includes forming a gate overlying at least one channel region in a semiconductor substrate, and forming spacers on a first portion of the semiconductor substrate self-aligned with the gate. A first dopant is implanted into the exposed portion of the semiconductor substrate for defining a body region of the transistor. The first dopant is implanted through a first implant window defined by the spacers. The spacers are removed, and a second dopant is implanted into the first portion of the semiconductor substrate for defining a source region of the transistor. The second dopant is implanted through a second implant window defined by an edge of the gate.

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Abstract: A stacked gate insulating film comprises a silicon oxide film and a tantalum oxide film which is stacked on the silicon oxide film and whose dielectric constant is higher than a dielectric constant of the silicon oxide film. The stacked gate insulating film is formed in accordance with the following steps. A semiconductor wafer is heated up, and the surface thereof is heat-oxidized. The silicon oxide film is formed on the semiconductor wafer (heat oxidation process). The silicon oxide film is etched back so as to be made thin (etch back process). The tantalum oxide film is stacked on the thin silicon oxide film (dielectric film formation process), thereby to form the stacked gate insulating film.

Abstract: A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

Abstract: A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

Abstract: A method (40) of forming an integrated circuit (60) device comprising a substrate (64). The method comprises the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack comprising a gate having sidewalls. The method further comprises the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further comprises the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer comprises depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.

Abstract: Disclosed is a method of manufacturing a semiconductor device including a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions formed to be adjacent to the gate electrode; and an Al wiring formed through an interlayer insulating film covering the gate electrode, wherein impurity ions are implanted in a surface layer of the substrate using the Al wiring and a photoresist formed thereon as a mask, and wherein no photoresist is formed on the Al wiring arranged above regions in which the impurity ions are implanted in adjacent elements.

Abstract: A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

Abstract: A method for fabricating a mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a thick oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the thick oxide layer. A portion of the thick oxide layer is then removed to expose the substrate, followed by forming a gate oxide layer on the exposed substrate surface for forming a plurality of coded memory cells, wherein the coded memory cells with a gate oxide layer corresponds to a logic state “1” while the code memory cells with a thick silicon oxide layer corresponds to a logic state “0”. A polysilicon layer is then formed on the substrate, followed by back-etching the polysilicon layer to expose the bar-shaped silicon nitride layer. After this, the bar-shaped silicon nitride layer is removed.

Abstract: A non-volatile semiconductor memory device includes an interlayer dielectric film 9, 19 flattened by etching back an SOG film. In the non-volatile semiconductor memory device, a barrier film of a silicon nitride film 9D and 19D is formed to cover at least a memory cell composed of a floating gate 4, a control gate 6, etc. Because of such a structure, even if H or OH contained in the SOG is diffused, it will not be trapped by a tunneling film 3. This improves a “trap-up rate”. The barrier film may be formed in only an area covering the memory cell. This reduces its contact area with a tungsten silicide film, thereby suppressing film peeling-off. Thus, the operation life of the memory cell in the non-volatile semiconductor memory device can be improved.

Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

Abstract: A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A method of fabricates a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, a gate oxide layer above the substrate and word lines formed above the gate oxide layer comprises: forming a dielectric layer over the word lines and gate oxide layer, forming and pattern first photoresist layer over the dielectric layer, etching the dielectric layer, stripping the first photoresist layer, forming and pattern second photoresist layer over the dielectric layer to develop an opening area for ion implantation, ion implanting a code implant dopant through the opening area down into the substrate and stripping the second photoresist layer.

Abstract: A method that includes: providing a substrate where a memory cell array region and a peripheral region are defined; forming a buried layer on the substrate; forming a gate material by positioning a gate insulating film on the substrate having the buried layer; forming first gates by covering the peripheral region, and etching the gate material of the memory cell array region according to a photolithography process; forming an insulating pattern on the substrate to fill up a space between the first gates and expose the surfaces of the first gates; forming second gates by covering the memory cell array region, and etching the gate material of the peripheral region according to the photolithography process; and forming a low resistance layer on the first gates, and simultaneously forming a source/drain at both sides of the second gates, by doping an impurity to the substrate having the first and second gates.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device includes a power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region with the opposite conductivity from the first; and an edge protection structure of substantial thickness and limited planar size incorporating at least one trench filled with dielectric material.

Abstract: A method of fabricating a mask read only memory. Embedded bit line are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The word line is perpendicular to the bit lines. The substrate under the word line and between each pair of the bit lines is referred as a memory unit. A first dielectric layer is formed to cover the substrate. A plurality of coding windows is formed in the first dielectric layer over the memory units. Ions are implanted into the memory cells exposed by the coding windows, and a second dielectric layer is formed to fill the coding windows.

Abstract: A method of forming multi-state mask ROM cells on a semiconductor substrate is disclosed. The method comprises following steps. Firstly, a pad oxide layer is formed on a semiconductor substrate. Then the pad oxide layer is patterned so as to form a plurality of first coding oxide regions. Thereafter, another photoresist pattern is formed to define buried bit line regions. A plurality of predetermined buried bit line regions are defined amid the first coding oxide regions. Then, a first ion implant by implanting n-type impurities into the semiconductor substrate using the photoresist pattern as a mask. After stripping the photoresist pattern, a first thermal oxidation is performed to grow oxide layer and driving the n-type impurities into the semiconductor substrate. Three types of oxide layer are formed with different thickness. Thereafter, a conductive layer are formed and then patterned as word lines. Subsequently, a photoresist pattern is formed to define second coding region.

Abstract: A manufacturing method of a MOS transistor. A gate oxide layer and a polysilicon layer are successively formed on a substrate. A nitrogen ion implantation is performed to implant nitrogen ions into the contact region of the polysilicon layer with the gate dielectric layer. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate. A dopant is implanted into the substrate on the sides of the gate, thereby forming a source/drain region.

Abstract: A method of forming and recognizing an identification mark for read-only memory. First, a first patterned resist layer is formed on a semiconductor substrate having an insulating region and a device region thereon by a code mask having code and identification mark patterns, and the identification mark pattern is over the insulating region. Next, ion implantation is performed to code in the device region. Thereafter, a second patterned resist layer is formed on the first patterned resist layer by a common mask to expose the entire identification mark pattern of the first patterned resist layer only. The identification mark pattern is then transferred to the insulating region by dry etching. Finally, the substrate having a clear identification mark is placed in an optical microscope for identification by an operator.

Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.

Abstract: A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).

Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.

Abstract: A thin film transistor and a method for fabricating the same are disclosed, in which an offset region is affected or biased by a gate voltage to increase on-current, thereby improving on/off characteristic of a device. A first semiconductor layer is formed on a substrate, and insulating layer patterns are formed at both ends of the first semiconductor layer. A second semiconductor layer is formed on the first semiconductor layer and the insulating layer patterns. A gate insulating film is formed on the first and second semiconductor layers and the insulating layer patterns, and an active layer formed on the gate insulating film.

Abstract: A plurality of diffusion layers extending in a first direction is formed at a surface of a semiconductor substrate in a cell region to be provided with the memory cell transistors. A plurality of gate electrodes extending in a second direction perpendicular to the first direction is formed on the semiconductor substrate in the cell regions. An interlayer insulating film is formed on the semiconductor substrate. A first resist film is formed on the interlayer insulating film. The first resist film is provided with openings in positions in alignment with regions between adjacent diffusion layers among the plurality of diffusion layers. a second resist film provided with openings previously designed in an arbitrary manner is formed on the first resist film. Then ions are implanted in the cell region using the first and second resist films as a mask.

Abstract: A split-gate p-channel memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a memory transistor and select transistor that share a common gate. It further includes two independent and distinct threshold voltage adjusts implanted in different portions of a channel region of a substrate of the memory cell. One of the threshold voltage adjusts is disposed in relation to the memory transistor so as to influence its threshold voltage. The other threshold voltage adjust is disposed in relation to the selected transistor so as to influence its threshold voltage. In the method of fabrication, an n-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the memory transistor and a p-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the select transistor.

Abstract: A method of forming a self-aligned mask ROM. Gate stacks that serve as word lines are formed over a substrate. Each gate stack includes a gate oxide layer, a gate conductive layer and a gate cap layer. Spacers are next formed on the sidewalls of the gate stacks. An insulation layer is deposited over the substrate and the gate stacks. The insulation layer is planarized to expose the gate cap layer. A patterned photoresist layer is formed over the insulation layer to expose the ion implant regions needed for programming. Using the patterned photoresist layer as an etching mask, the gate cap layer within each ion implant region is removed to expose the gate conductive layer using an etchant with high etching selectivity. Using the patterned photoresist layer as an implant mask, ions are implanted into the substrate via the ion implant regions so that the mask ROM is programmed. Finally, the photoresist layer is removed.

Abstract: The semiconductor device is provided with an element isolating region disposed in a matrix to define a channel region on a semiconductor substrate, gate interconnection layers extending in a direction and disposed at predetermined intervals from each other above element isolating region, and aluminum interconnection layers extending in a direction intersecting gate interconnection layers and disposed at predetermined intervals from each other, aluminum interconnection layer being disposed above element isolating region. Thus, it becomes possible to provide a semiconductor device and a method of manufacturing thereof which enable the reduction in time required for the final manufacturing steps of the semiconductor device after the ROM specifications are determined.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines a connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material.

Abstract: A method of fabricating self-aligned multilevel mask read only memory (ROM). The method can improve the process window to reduce process difficulty by utilizing the self-aligned implantation. Moreover, by utilizing the connection between the word line and the gate and implantation of the ROM code with self-aligned implatiation to increase the difference between the threshold voltages of different gates, and therefore, multilevel cell transistors with for the mask ROM with multilevel threshold voltages are formed to times the capacity of the mask ROM.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: A method of fabricating self-aligned multilevel mask read only memory (ROM). The method can improve the process window to reduce process difficulty by utilizing the self-aligned implantation. Moreover, by utilizing the height difference between different gate polysilicon layers and implantation of the ROM code with self-aligned implatiation to increase the difference between the threshold voltages of different gates, and therefore, multilevel cell transistors with for the mask ROM with multilevel threshold voltages are formed to times the capacity of the mask ROM.

Abstract: Source/drain regions of an MOS transistor are formed at a surface of a p-type silicon substrate. A storage node electrically connected to the source/drain regions penetrates a bit line to reach the n-type source/drain region. The storage node and the bit line are insulated from each other by a sidewall insulating layer. Thus, a semiconductor memory device suitable for high integration is obtained in which short-circuit between the storage node and the bit line on a gate electrode layer can be prevented.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate electrodes are formed via a gate oxide film and then sidewall oxide films are formed, on the semiconductor substrate. Thereafter, an ion implantation of a P-type impurity is performed with a dose two orders of magnitude smaller than that of the N-type impurity for element isolation, with the gate electrodes and the sidewall oxide films being employed as a mask, thereby forming P-type impurity regions. The P-type impurity regions are caused to diffuse due to thermal processing in the following step. However, the element isolating P-type impurity regions resulted from the diffusion diffuse only into immediately under the sidewall oxide films at most, thus preventing the channel width from being narrowed.

Abstract: A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device so as to dope portions of the sidewall spacers on one side of each of the digit lines while sidewall spacers opposed thereto and adjacent bit contacts are shielded from the dopant. Doped regions of the sidewall spacers may be removed with selectivity over undoped regions thereof to expose connect regions of each conductive element of each digit line. A conductive strap may then be formed to electrically link each connect region to its corresponding bit contact. Semiconductor devices including the conductive straps are also disclosed.

Abstract: A method of fabricates a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, a gate oxide layer above the substrate and word lines formed above the gate oxide layer comprises: forming a dielectric layer over the word lines and gate oxide layer, forming and pattern first photoresist layer over the dielectric layer, etching the dielectric layer, stripping the first photoresist layer, forming and pattern second photoresist layer over the dielectric layer to develop an opening area for ion implantation, ion implanting a code implant dopant through the opening area down into the substrate and stripping the second photoresist layer.

Abstract: The invention provides a method for forming a ROM cell surface implant region using a PLDD implant. A semiconductor structure is provided comprising a substrate having isolation structures thereon, which separate and electrically isolating a first area having a P-well formed in the substrate and a gate over the substrate, a second area having a N-well formed in the substrate and a gate over the substrate, and a third area having P-well and buried N+ regions formed in the substrate with second isolation structures overlying the buried N+ regions. A photoresist mask is formed exposing the first area, and impurity ions are implanted to form n-type lightly doped source and drain regions. The photoresist mask is removed and a new (PLDD/ROM) photoresist mask is formed exposing the second area and the third area. Impurity ions are implanted to simultaneously form p-type lightly doped source and drain regions and a ROM cell surface implant region region. The PLDD/ROM photoresist mask is then removed.

Abstract: A semiconductor device e.g. a gate array, a mask ROM or the like produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device, wherein the upper-layer interconnections are connected exclusively with the selected ones of the foregoing units and are isolated from the unselected ones of the foregoing units, by a space or an insulator layer produced between the upper-layer interconnection and a layer in which conductive paths are produced for connecting the upper-layer interconnection and the foregoing units.

Abstract: A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced. As a result, the word lines can be formed with minimum grid spacing and the risk of short-circuiting between adjacent word lines is eliminated by buried ploy stringers.

Abstract: A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then removed and a neutral ion species such as Silicon or Germanium is implanted between the source and drain regions in the region that is to become the doped channel region. A dopant substance is next implanted into the channel region, which is then exposed to ultra-rapid thermal annealing to cause the dopant to form a box-like, super-steep retrograded channel profile. The gate is then re-formed over the now activated doped channel region.