Abstract: When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the sensitive gate materials may be improved by reducing the depth of or eliminating recessed areas that are obtained after forming sophisticated trench isolation regions. To this end, after completing the STI module, an additional fill material may be provided so as to obtain the desired surface topography and also preserve superior material characteristics of the trench isolation regions.

Abstract: An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

Abstract: A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the substrate under the first film, and first epitaxial crystal layers formed on both sides of the first channel region in the substrate, the first layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the substrate via a second gate insulating film, a second channel region formed in the substrate under the second film, second epitaxial crystal layers formed on both sides of the second channel region in the substrate, and third epitaxial crystal layers formed on the second layers, the second layers comprising a second crystal, the third layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer.

Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.

Abstract: A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.

Abstract: A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

Abstract: Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.

Abstract: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.

Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

Abstract: Disclosed is a field effect transistor (FET), in which ohmic body contact(s) are placed relatively close to the active region. The FET includes a semiconductor layer, where the active region and body contact region(s) are defined by a trench isolation structure and where a body region is below and abuts the active region, the trench isolation structure and the body contact region(s). A gate traverses the active region. Dummy gate(s) are on the body contact region(s). A contact extends through each dummy gate to the body contact region below. Dielectric material isolates the contact(s) from the dummy gate(s). During processing, the dummy gate(s) act as blocks to ensure that the body contact regions are not implanted with source/drain dopants or source/drain extension dopants and, thereby to ensure that the body contacts, as formed, are ohmic. Also disclosed are an integrated circuit structure with stacked FETs, having such ohmic body contacts, and associated methods.

Abstract: A semiconductor device having high aspect ratio isolation trenches and a method for manufacturing the same is presented. The semiconductor device includes a semiconductor substrate, a first insulation layer, and a second insulation layer. The semiconductor substrate has a second trench that is wider than a first trench. The first insulation layer is partially formed within the wider second trench in which the first insulation layer when formed clogs the opening of the narrower first trench. A cleaning of the first insulation layer unclogs the opening of the narrower first trench in which a second insulation layer can then be formed within both the first and second trenches.

Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract: A method for fabricating a semiconductor device, including (a) etching a semiconductor substrate to form a first trench defining an active region; (b) forming a first spacer on sidewalls of the first trench; (c) etching a bottom of the first trench to form a second trench; (d) etching a sidewall of the second trench to form a third trench including an undercut space; (e) forming a device isolation structure that fills the first, second and third trenches; (f) etching the semiconductor substrate of a gate region to form a recess; and (g) forming a gate that fills the recess.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

Abstract: A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.

Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.

Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.

Abstract: An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.

Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.

Abstract: A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation layers, forming a plurality of second trenches on a second region of the semiconductor substrate, and filling the second trenches with a second insulation material different from the first insulation material to form second device isolation layers, wherein the first trenches and the second trenches are formed using different respective processes.

Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: A method for fabricating shallow trench isolation structures is provided. A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate includes a memory region and a periphery region. By using the patterned mask layer as a mask, the substrate is partially removed to form a plurality of trenches. A first liner layer is formed on the substrate to cover surfaces of the patterned mask layer, the patterned pad layer and the trenches. After removing the first liner layer in the periphery region, a pull-back process is performed on the patterned mask layer, and a pull-back amount of the patterned mask layer in the periphery region is larger than a pull-back amount of the patterned mask layer in the memory region. An insulating layer is formed in the trenches to form a plurality of shallow trench isolation structures.

Abstract: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).

Abstract: A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.

Abstract: A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Abstract: An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field plates with a trench gate structure are arranged in the cell field, and an edge trench surrounding the cell field is provided in the edge region. The front side of the semiconductor body is in the edge region provided with an edge zone of a conduction type complementing the first conduction type with doping materials of body zones of the cell field. The edge zone of the complementary conduction type extends both within and outside the edge trench.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

Abstract: A method of manufacturing a semiconductor device (1200), the method comprising forming a sacrificial pattern having a recess on a substrate (402), filling the recess and covering the substrate and the sacrificial pattern with a semiconductor structure, forming an annular trench in the semiconductor structure to expose a portion of the sacrificial pattern and to separate material (904) of the semiconductor structure enclosed by the annular trench from material (906) of the semiconductor structure surrounding the annular trench, removing the exposed sacrificial pattern to expose material of the semiconductor structure filling the recess, and converting the exposed material of the semiconductor structure filling the recess into electrically insulting material (1202).

Abstract: Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

Abstract: By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.