Abstract: A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.

Abstract: A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the damascene material. Copper-comprising material is electrochemically deposited over the damascene material. The copper-comprising material is removed and the damascene material is exposed, and individual copper-comprising conductive lines are formed within individual of the line trenches. The damascene material is removed selectively relative to the conductive copper-comprising material. Dielectric material is deposited laterally between adjacent of the individual copper-comprising conductive lines. The deposited dielectric material is received against sidewalls of the individual copper-comprising conductive lines. A void is received laterally between immediately adjacent of the individual copper-comprising conductive lines within the deposited dielectric material. Other embodiments are contemplated.

Abstract: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The shallow trench isolaton structures are formed by dielectric material filling trenches that are formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is blanket deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels and the mandrels are subsequently removed, thereby leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the shallow trench isolaton structures. The substrate is doped to form source, drain and channel regions and a gate is formed over the channel region.

Abstract: A polysilicon film is formed all over a surface of a semiconductor substrate, then is subject to a CMP process through a mask pattern as a stopper. Then, a metal film is formed all over the resulting surface, and is allowed at least a part of the polysilicon film and at least a part of the metal film to react with each other to silicidize the metal. This forms the gate electrode.

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Abstract: An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

Abstract: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.

Abstract: A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface.

Abstract: An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region 3 in a substrate 1 including a silicon layer at least in a surface thereof and filling a first insulator in the device isolation region 3, a step of making height of an upper surface of the first insulator less than height of an upper surface of the substrate 1 and forming a sidewall film 10 on a sidewall of the device isolation region 3, and a step of depositing a metallic film 11 on the substrate 1 and then conducting silicidation through a thermal process.

Abstract: A method of fabricating a semiconductor device, comprises steps of forming a common contact hole for a first conductivity-type region and a second conductivity-type region, implanting an impurity in at least one of the first conductivity-type region and the second conductivity-type region, and forming a shared contact plug by filling an electrical conducting material in the contact hole, wherein in the implanting step, an impurity is implanted in at least one of the first conductivity-type region and the second conductivity-type region such that the first conductivity-type region and the shared contact plug are brought into ohmic contact with each other, and the second conductivity-type region and the shared contact plug are brought into ohmic contact with each other.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.

Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.

Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating fil

Abstract: A method of manufacturing semiconductor devices includes forming a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer on a semiconductor substrate, forming a first trench in the semiconductor substrate by partially etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate, forming a first ion implantation region having a first impurity concentration into the semiconductor substrate of inner walls of the first trench by performing a first ion implantation process, forming a second trench extending from the first trench by etching the semiconductor substrate of a bottom of the first trench, and forming a second ion implantation region having a second impurity concentration lower than the first impurity concentration into the semiconductor substrate of inner walls of the second trench by performing a second ion implantation process, wherein a depth of the first trench is shallower than that of a juncti

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).

Abstract: A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the silicon nitride layer (96), and polishing and densifying the protective dielectric layer (97, 98) to thereby form a densified silicon nitride encapsulation layer (99) over the shallow trench isolation region (95).

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode.

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

Abstract: In manufacturing processes of a semiconductor device including a shallow trench element isolation region and an interlayer insulating film of a multilayer structure, it is necessary to repeatedly use CMP, but since the CMP itself is costly, the repeated use of the CMP is a cause to increase the manufacturing cost. As an insulating film for use in a shallow trench (ST) element isolation region and/or a lowermost-layer interlayer insulating film, use is made of an insulating coating film that can be coated by spin coating. The insulating coating film has a composition expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x(where n=1 to 3 and 0?x?1.0) and a film with a different relative permittivity k is formed by selecting heat treatment conditions. The STI element isolation region can be formed by modifying the insulating coating film completely to a SiO2 film, while the interlayer insulating film with a small relative permittivity k can be formed by converting it to a state not completely modified.

Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.

Abstract: An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved.

Abstract: Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: Disclosed is a semiconductor device that comprises a first semiconductor layer of one conductivity type provided on a substrate; a second semiconductor layer of the one conductivity type provided on the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; an isolation region extending from one principal face of the second semiconductor layer to reach the substrate; a first region in an element region of the second semiconductor layer isolated by the isolation region and having an opposite conductivity type; a second region of the one conductivity type provided in the element region extending from the one principal face to reach the first semiconductor layer and having an impurity concentration higher than the second semiconductor layer; and an insulation region extending from the one principal face to the first semiconductor layer, kept away from the substrate, and provided between the first and the second regions.

Abstract: A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench.

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

Abstract: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film.

Abstract: A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift regions between the gate electrode and the source or drain region, wherein the drift regions comprise first and second conductivity-type impurities.

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth.

Abstract: A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 500 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.