Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.

Abstract: A highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics is manufactured. In the semiconductor device which includes an inverted-staggered transistor having a bottom-gate structure and being provided over a substrate having an insulating surface, at least a first gate insulating film and a second gate insulating film are provided between a gate electrode layer and an oxide semiconductor film, and heat treatment is performed at a temperature of 450° C. or higher, preferably 650° C. or higher, and then the oxide semiconductor film is formed. By the heat treatment at a temperature of 450° C. or higher before the formation of the oxide semiconductor film, diffusion of hydrogen elements into the oxide semiconductor film, which causes degradation or variations in electric characteristics of the transistor, can be reduced, so that the transistor can have stable electric characteristics.

Abstract: Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel.

Abstract: Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects.

Abstract: A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material.

Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.

Abstract: Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.

Abstract: One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.

Abstract: Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition.

Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

Abstract: A method of forming a semiconductor device may include forming a metal layer on a silicon portion of a substrate, and reacting the metal layer with the silicon portion to form a metal silicide. After reacting the metal layer, unreacted residue of the metal layer may be removed using an electrolyzed sulfuric acid solution. More particularly, a volume of sulfuric acid in the electrolyzed sulfuric acid solution may be in the range of about 70% to about 95% of the total volume of the electrolyzed sulfuric acid solution, a concentration of oxidant in the electrolyzed acid solution may be in the range of about 7 g/L to about 25 g/L, and a temperature of the electrolyzed sulfuric acid solution may be in the range of about 130 degrees C. to about 180 degrees C.

Abstract: A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. Trenches are etched through a pre-metal dielectric to the contacts of the FET. Etching extends further into the substrate, through the surface silicon layer, through the silicon germanium layer and into the substrate below the silicon germanium layer. The further etch is performed to a depth to allow for sufficient edge relaxation to induce a desired level of longitudinal strain to the surface layer of the FET. Subsequent processing forms contacts extending through the pre-metal dielectric and at least partially into the trenches within the substrate.

Abstract: A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.

Abstract: A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel to a top surface of the gate dielectric region. After the atom implantation, a conformal dielectric layer is formed on top and side walls of the gate electrode region. A dielectric spacer layer, formed on the conformal dielectric layer, is etched such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to a reference direction intersects the conformal dielectric layer. The reference direction is perpendicular to the top surface of the gate dielectric region.

Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

Abstract: An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure.

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.

Abstract: A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.

Abstract: An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The second semiconductor material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the first semiconductor material, and the first semiconductor material is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the second semiconductor material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.

Abstract: A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.

Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.

Abstract: A stressed single crystalline epitaxial semiconductor layer having a first type stress is formed on a single crystalline substrate layer. First and second semiconductor fins are formed by patterning the stressed single crystalline epitaxial semiconductor layer. A center portion of each first semiconductor fin is undercut to form a recessed region, while the bottom surface of each second semiconductor fin maintains epitaxial registry with the single crystalline substrate layer. The center portion of each first semiconductor fin is under a second type of stress, which is the opposite of the first type of stress. A first field effect transistor formed on the first semiconductor fins can include first channels under the second type of stress along direction of current flow, and a second field effect transistor formed on the second semiconductor fins can include second channels under the first type of stress along the direction of current flow.

Abstract: Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition.

Abstract: One illustrative method disclosed herein involves forming gate structures for first and second spaced-apart transistors above a semiconducting substrate, forming an etch stop layer above the substrate and the gate structures, performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer, after performing at least one angled ion implant process, forming a layer of insulating material above the etch stop layer, performing at least one first etching process to define an opening in the layer of insulating material and thereby expose a portion of the etch stop layer, performing at least one etching process on the exposed portion of the etch stop layer to define a contact opening therethrough that exposes a doped region formed in the substrate, and forming a conductive contact in the opening that is conductively coupled to the doped region.

Abstract: A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.

Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

Abstract: Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.