Abstract: A semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; an insulation film formed between the source electrode and the drain electrode and having a band-like opening in parallel to the source electrode and the drain electrode; a gate electrode formed at the opening in the insulation film; and a drain-side field plate electrode formed integrally with the gate electrode on the drain electrode side of the gate electrode and having a drain electrode side end portion spaced from the insulation film, thus restraining degradation in performance.

Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Abstract: Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

Abstract: A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

Abstract: In the device, first and second transistors have first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface if the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than the longitudinal direction width of the first bottom. The high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom in the longitudinal direction is larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.

Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.

Abstract: A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a second well, implanting second conduction type impurities into the second well to form an impurity region, forming a gate on the semiconductor substrate, and implanting second conduction type impurities to form a drain region in the impurity region on one side of the gate.

Abstract: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.

Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.

Abstract: A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patterning the hard mask layer to from a hard mask pattern; forming a spacer layer over the hard mask pattern; etching back the spacer layer to form spacers over sidewalls of the hard mask pattern; etching the gate material layers by using the spacers and the hard mask pattern as an etching mask to form a gate structure; and performing a tilt-angle ion implantation process to the semiconductor substrate.

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract: Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers laterally adjacent the gate stack. The method further includes the steps of amorphizing the S/D regions, depositing a silicide-forming material over the amorphized S/D regions, and heating the partially-completed semiconductor device to a predetermined temperature at which the silicide-forming material reacts with the amorphized S/D regions.

Abstract: Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

Abstract: A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.

Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract: The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region.

Abstract: A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.

Abstract: A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed.

Abstract: Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patterning the hard mask layer to from a hard mask pattern; forming a spacer layer over the hard mask pattern; etching back the spacer layer to form spacers over sidewalls of the hard mask pattern; etching the gate material layers by using the spacers and the hard mask pattern as an etching mask to form a gate structure; and performing a tilt-angle ion implantation process to the semiconductor substrate.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.

Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack.

Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.

Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

Abstract: First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first indices being inclined from a normal direction of a surface of the second evaluation substrate. Ion implantation is performed for the first evaluation substrate in a vertical direction. Ion implantation is performed for the second evaluation substrate by using an ion beam parallel to the direction defined by the first indices. Impurity concentration distributions in a depth direction of the first and second evaluation substrates are measured. A first impurity concentration distribution on an extension line of an ion beam and a second impurity concentration distribution in a direction perpendicular to the extension line are predicted from the measured impurity concentration distributions of the first and second evaluation substrates.

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation.

Abstract: A method for fabricating a semiconductor device is disclosed.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.

Abstract: A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate electrode is formed over the semiconductor substrate in the first region. A first photoresist film covering the second region and having an opening exposing the first active region and having an edge on the border portion of the opening positioned nearer the second active region than a middle of the device isolation film is formed over the semiconductor substrate with the gate electrode. Impurity ions are implanted from a direction tilted from a normal direction of the semiconductor substrate with the first photoresist film and the gate electrode as a mask to form pocket regions in the semiconductor substrate on both sides of the gate electrodes.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.

Abstract: In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is provided, which is, in combination with a dielectric cap material, also used as an efficient implantation mask during the implantation of extension and halo regions, thereby increasing the ion blocking capability of the complex gate electrode structure substantially without affecting the sensitive gate materials.

Abstract: One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, including introducing a first dopant into a first partial completion of the device, the first dopant including a first noise reducing species; and introducing a second dopant into a second partial completion of the device, the second dopant and the first dopant being opposite conductivity types.

Abstract: A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation.

Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

Abstract: A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

Abstract: A method for fabricating a NOR semiconductor memory structure includes: performing a deeply doped source ion implantation process and a lightly doped drain ion implantation process; forming oxide layer walls on two said sides of a gate structure, respectively; performing a pocket implant process with control of an incident angle thereof; and performing a deeply doped drain ion implantation process. Characteristics of the NOR semiconductor memory structure are improved by controllably changing the position of a pocket implant region.

Abstract: The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer.