Abstract: A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is conformally formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole.

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract: A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process.

Abstract: Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.

Abstract: Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract: A method of forming an integrated circuit comprises forming at least one gate electrode of at least one active transistor, and at least one first dummy gate electrode. The method also comprises forming a first doped region disposed in the substrate and adjacent to a first side wall of the at least one first dummy gate electrode, wherein the first doped region has a first conductivity type dopant. The method further comprises forming a second doped region disposed in the substrate and adjacent to a second side wall of the at least one first dummy gate electrode. The second doped region has a second conductivity type dopant that is opposite to the first conductivity type dopant.

Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.

Abstract: The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.

Abstract: Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate.

Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: A method of manufacturing a semiconductor device, the semiconductor device including a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Abstract: A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness.

Abstract: A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A dummy gate can establish the position of the abrupt interfaces and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel, or to overlap the extension tip.

Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Abstract: When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.

Abstract: Provided is a semiconductor device with improved performance and production yield. Insulating films IL2 and IL3 are formed over a semiconductor substrate in that order to cover a gate electrode. Then, the insulating films IL3 and IL2 are etched back to form sidewall spacers including the insulating films IL2 and IL3 over sidewalls of the gate electrode. The source/drain region is formed in the semiconductor substrate by ion implantation using the gate electrode and the sidewall spacer as a mask. Then, the sidewall spacers are isotropically etched on conditions where the insulating film IL2 is less likely to be etched than the third insulating film IL3 to thereby decrease the thickness of the sidewall spacer. Thereafter, a reaction layer between the metal and the source/drain region is formed over the source/drain region.

Abstract: Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

Abstract: A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench.

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.

Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract: A light-emitting device having at least one spacer located at a bottom surface is disclosed. In two other embodiments, an electronic display system and an electronic system having such light-emitting device are disclosed. The light-emitting device comprises a plurality of leads, a light source die, and a body. The body encapsulates a portion of the plurality of leads and the light source die. The body has a least one side surface and a bottom surface. The at least one spacer is located at the bottom surface. In use, the light-emitting device is attached to a top surface of a substrate. The spacer is configured to create an air vent between the bottom surface and the top surface of the substrate when the light-emitting device is attached to, and the spacer is in contact with the substrate.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass transition temperature (Tg,O) and a degradation temperature (Td). A temperature window may be defined to correspond to temperatures (T) within the range of Tg,O?T?Td. While the block copolymer is in the upper half of the temperature window, solvent may be dispersed into the block copolymer to a process volume fraction that induces self-assembly of the block copolymer into a pattern. A defect specification may be defined, and the process volume fraction of solvent may be at level that achieves self-assembly within the defect specification. In some embodiments, the solvent may be removed from within the block copolymer while maintaining the defect specification.

Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.

Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.

Abstract: A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.

Abstract: Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor film, and a second polysilicon film, reduction in resistance of a normally-off transistor and reduction in resistance of a lower electrode of the capacitor are simultaneously performed, and reduction in resistance of an N-type MOS transistor and reduction in resistance of an upper electrode of the capacitor are simultaneously performed.

Abstract: A method of manufacturing a semiconductor device includes the steps of: providing a supply of molecules containing a plurality of dopant atoms into an ionization chamber, ionizing said molecules into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ions by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant molecules contain n dopant atoms, where n is an integer number greater than 10. This method enables increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy, while reducing the charge per dopant atom by the factor n.