Abstract: A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.

Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.

Abstract: The method of manufacturing a semiconductor device selectively forms a resist film on the multilayer gate film and the gate side wall insulating film extending on the semiconductor substrate. An upper part of the gate side wall insulating film and the hard mask film selectively are removed by etching using the resist film as a mask so as to expose a surface of the metal film. the metal film and the barrier metal film adjoining the metal film are removed, by wet etching. After the removal of the resist film, embedding a space formed by removal of the metal film and the barrier metal film and depositing a pre-metal dielectric to a level higher than an upper surface of the remaining hard mask film. A top part of the pre-metal dielectric is planarized by CMP using the remaining hard mask film as a stopper.

Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate.

Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The resistor pattern includes resistors, and a connection structure connecting the resistors in series. The resistors is arranged in matrix of two or more rows and two or more columns. The method includes further heating the resistor pattern by scanning the resistor pattern with a second beam having a different scan direction as that of the first beam.

Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.

Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.

Abstract: One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.

Abstract: According to one embodiment, a memory includes a resistance change element on an interlayer insulating film and including a lower electrode and an upper electrode, a sidewall insulating film on a side surface of the element, a plug in the interlayer insulating film and connected to the lower electrode, an interconnect on the interlayer insulating film and connected to the upper electrode. The element is provided immediately above the plug, the interconnect covers the side surface of the element via the sidewall insulating film, an upper surface of the first plug is covered with the lower electrode and the sidewall insulating film.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.

Abstract: A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.

Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.

Abstract: According to one embodiment, a memory device includes a first electrode, a first resistance change layer, a first insulating section, a second electrode and an intermediate layer. The first resistance change layer is provided on the first electrode. The first insulating section is provided on the first resistance change layer. The second electrode is provided on the first resistance change layer. The second electrode is in contact with the first resistance change layer. The intermediate layer is provided between the second electrode and the first insulating section. The intermediate layer is in contact with the second electrode and the first insulating section.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

Abstract: A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer. The second variable resistance layer is formed to cover the step and have, above the step, a bend covering the step. The bend, seen from above, has only one corner in a surface of the second variable resistance layer.

Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.

Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

Abstract: First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Abstract: Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

Abstract: Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured. In some embodiments, the metal-rich host oxide is deposited using a modified atomic layer deposition (ALD) process. In other embodiments, the metal-rich host oxide is formed by depositing a metal-containing coupling layer on a host oxide and thermally processing both layers to create a metal-rich composite host oxide with a higher concentration of oxygen vacancies.

Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a dielectric structured as an operably variable resistance region between an oxygen source and an oxygen sink. The dielectric, oxygen source, and an oxygen sink can be structured as a field driven unipolar memory element with respect to generation and healing of a filament in the dielectric. Additional apparatus, systems, and methods are disclosed.

Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.

Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract: In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures.

Abstract: To provide a semiconductor device having a structure free from variations in resistance even when a stress is applied thereto; and a manufacturing method of the device. The semiconductor device has a metal resistor layer in a region between a passivation film and an uppermost level aluminum interconnect. This makes it possible to realize a high-precision resistor having few variations in resistance due to a mold stress that occurs in a packaging step or thereafter and therefore, makes it possible to form a high-precision analog circuit.

Abstract: Provided are methods for etching resistive switching and electrode layers in resistive random access memory (ReRAM) cells. Both types of layers are etched in the same operation. This approach simplifies processing in comparison to conventional etching, in which each layer is etched individually. The composition of etchants and process conditions are specifically selected to provide robust and effective etching of both types of layers. The two etching rates may be comparable and may be substantially the same, in some embodiments. Plasma etching involving tri-fluoro-methane and oxygen containing etchants may be used on electrode materials, such as titanium nitride, platinum, and ruthenium, and on resistive switching materials, such as oxides of transition metals. For example, a combination of titanium nitride and hafnium oxide may be etched using such processes. In some embodiments, an etched stack includes a third layer, which may function as a current limiter in ReRAM cells.

Abstract: A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction.

Abstract: A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.

Abstract: A phase change material may be processed to reduce its microcrystalline grain size and may also be processed to increase the crystallization or set programming speed of the material. For example, material doped with nitrogen to reduce grain size may be doped with titanium to reduce crystallization time.

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.

Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.

Abstract: An optically transparent memory device comprises first and second electrodes, wherein the electrodes are formed from conductive material(s) that is transparent. The memory device also provides a resistive memory layer coupled to the first and second electrodes. The resistive memory layer is formed from a resistive memory material providing resistive switching that is transparent. Additionally, the optically transparent memory device may be incorporated into a variety of electronics.

Abstract: Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.