Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.

Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

Abstract: A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.

Abstract: A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL.

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract: A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.

Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

Abstract: A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a stopper film on the memory cell layer. The method of manufacturing a semiconductor storage device also includes: etching the stopper film, the memory cell layer, and the first wiring layer; polishing an interlayer insulating film to the stopper film after burying the stopper film, the memory cell layer, and the first wiring layer with the interlayer insulating film; performing a nitridation process to the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film, respectively; and forming a second wiring layer on the adjustment film, the second wiring layer being electrically connected to the adjustment film.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.

Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2? ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x<3).

Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Abstract: Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx>n is satisfied.

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.

Abstract: According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Abstract: Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing. At least one electrode in a memory element is reactive, while another may be inert. The precursor layer is converted into a resistance switching layer as a result of this diffusion. The precursor layer may initially include a stoichiometric oxide that generally does not exhibit resistance switching characteristics until oxygen vacancies are created. Metals forming such oxides may be more electronegative than metals forming a reactive electrode. The reactive electrode may have substantially no oxygen at least prior to annealing. Annealing may be performed at 250-400° C. in the presence of hydrogen. These methods simplify process control and may be used to form nonvolatile memory elements including resistance switching layers less than 20 Angstroms thick.

Abstract: A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Abstract: A phase-change random access memory device and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a heating electrode, forming an interlayer insulating layer including a preliminary phase-change region on the semiconductor substrate, reducing a diameter of an inlet portion of the preliminary phase-change region to be smaller than that of a bottom portion of the preliminary phase-change region, filling an insulating layer having a void in the preliminary phase-change region using a difference between the diameter of the inlet portion and the diameter of the bottom portion, removing the insulating layer to an interface between the inlet portion and the bottom portion, thereby forming a key hole exposing the heating electrode, and forming a phase-change material layer to be buried in the key hole and the preliminary phase-change region.

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract: Provided are resistive random access memory (ReRAM) cells having switching layers that include hafnium, aluminum, oxygen, and nitrogen. The composition of such layers is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. In some embodiments, the concentration of nitrogen in a switching layer is between about 1 and 20 atomic percent or, more specifically, between about 2 and 5 atomic percent. Addition of nitrogen helps to control concentration and distribution of defects in the switching layer. Also, nitrogen as well as a combination of two metals helps with maintaining this layer in an amorphous state. Excessive amounts of nitrogen reduce defects in the layer such that switching characteristics may be completely lost. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).

Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract: Provided are carbon doped resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming thereof. Carbon doping of metal containing materials creates defects in these materials that allow forming and breaking conductive paths as evidenced by resistive switching. Relative to many conventional dopants, carbon has a lower diffusivity in many suitable base materials. As such, these carbon doped materials exhibit structural stability and consistent resistive switching over many operating cycles. Resistive switching layers may include as much as 30 atomic percent of carbon, making the dopant control relatively simple and flexible. Furthermore, carbon doping has acceptor characteristics resulting in a high resistivity and low switching currents, which are very desirable for ReRAM applications. Carbon doped metal containing layer may be formed from metalorganic precursors at temperatures below saturation ranges of atomic layer deposition.

Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Abstract: A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.

Abstract: A reprocessing method of a semiconductor device, the reprocessing method includes adjusting a resistance value of a first resistor by first trimming the first resistor, wherein the first resistor is electrically connected between a first pad and a second pad, forming a second resistor on the first trimmed first resistor, and adjusting a resistance value of the second resistor by second trimming the second resistor.

Abstract: To provide a resistance change element which does not require a forming process and enables reduction of power consumption and miniaturization of the element, and to provide a method for producing it. A resistance change element 1 according to an embodiment of the present invention includes a bottom electrode layer 3, a top electrode layer 5 and an oxide semiconductor layer 4. The oxide semiconductor layer 4 has a first metal oxide layer 41 and a second metal oxide layer 42. The first metal oxide layer 41 is formed between the bottom electrode layer 3 and the top electrode layer 5, and in ohmic contact with the bottom electrode layer 3. The second metal oxide layer 42 is formed between the first metal oxide layer 41 and the top electrode layer 5, and in ohmic contact with the top electrode layer 5.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell.

Abstract: A method for fabricating a variable resistance memory device includes forming an oxygen-deficient first metal oxide layer over a first electrode, forming an oxygen-rich second metal oxide layer over the first metal oxide layer, treating the first and second metal oxide layers with hydrogen-containing plasma, forming an oxygen-rich third metal oxide layer, and forming a second electrode over the third metal oxide layer.

Abstract: A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. The diode line and the projection are formed of a single layer to be in continuity with each other.

Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.