Groove Formation Patents (Class 438/42)
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Publication number: 20120088323Abstract: A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer.Type: ApplicationFiled: September 23, 2011Publication date: April 12, 2012Inventors: DAE-LOK BAE, Byung-Lyul Park, Pil-Kyu Kang, Gil-Heyun Choi, Kwang-Jin Moon
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Publication number: 20120074398Abstract: An organic EL illuminant (20) includes a first electrode (22), an organic EL layer (23), and a second electrode (24) which are sequentially stacked on a supporting base (21), wherein when a side in which the supporting base (21) is provided is one side, and a side in which the second electrode (24) is provided is the other side, a surface of the one side of at least one of the supporting base (21), the first electrode (22), or the second electrode (24) is larger than a surface of the other side of the at least one of the supporting base (21), the first electrode (22), or the second electrode (24).Type: ApplicationFiled: March 11, 2010Publication date: March 29, 2012Applicant: Sharp Kabushiki KaishaInventor: Yoshimasa Fujita
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Publication number: 20120068196Abstract: A semiconductor light-emitting device comprises a semiconductor layer structure disposed over a substrate. The layer structure includes an active region disposed between a first layer and a second layer. One or more cavities are present in the layer structure, each cavity being coincident with a threading dislocation and extending from an upper surface of the layer structure through at least the second layer and the active region. Removing material where a threading dislocation is present provides effective suppression of the tendency of the threading dislocations to act as non-radiative centres, thereby improving the light output efficiency of the device. The device may be manufactured by a first step of selectively etching the layer structure at the locations of one or more threading dislocation to form a pilot cavity at the or each location. A second etching step is applied to increase the depth of each pilot cavity.Type: ApplicationFiled: September 9, 2011Publication date: March 22, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Tim Michael SMEETON, Mathieu Xavier SENES, Wei-Sin TAN, Valerie BERRYMAN-BOUSQUET
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Publication number: 20120070927Abstract: A method for producing an optoelectronic semiconductor component includes providing a first wafer having a patterned surface, wherein the patterned surface is formed at least in places by elevations having first and second heights, wherein the first height is greater than the second height; providing a second wafer; applying a photoresist to outer areas of the second wafer; patterning a surface of the photoresist facing away from the second wafer by impressing the patterned surface of the first wafer into the photoresist, wherein the elevations are impressed as trenches having a first and second depth into the photoresist; applying a patterning method to the patterned surface of the photoresist, wherein the structure applied on the photoresist is transferred at least in places to the outer area of the second wafer.Type: ApplicationFiled: May 3, 2010Publication date: March 22, 2012Applicant: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Elmar Baur, Alexander Heindl, Bernd Böhm, Patrick Rode, Heribert Zull
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Patent number: 8137995Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.Type: GrantFiled: December 11, 2008Date of Patent: March 20, 2012Assignee: STATS ChipPAC, Ltd.Inventors: OhHan Kim, JoungUn Park, SunMi Kim
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Patent number: 8139619Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.Type: GrantFiled: August 12, 2011Date of Patent: March 20, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Patent number: 8138003Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.Type: GrantFiled: February 21, 2011Date of Patent: March 20, 2012Assignee: Siltron, Inc.Inventors: Doo-Soo Kim, Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee
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Patent number: 8133803Abstract: A method for fabricating a semiconductor layer comprising: a) growing a semiconductor layer on a foreign substrate; b) forming at least one opening on the semiconductor layer, wherein the opening exposes the interface between the semiconductor layer and the foreign substrate; and c) removing at least part of the semiconductor solid state material along the interface between the semiconductor layer and the foreign substrate. The removing step c) is preferably achieved by selective interfacial chemical etching. The semiconductor layer may be utilized as a substrate for fabrication of a wide variety of electronic and opto-electronic devices and integrated circuitry products.Type: GrantFiled: June 23, 2009Date of Patent: March 13, 2012Assignee: Academia SinicaInventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-Chung Kuo
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Patent number: 8134223Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.Type: GrantFiled: November 13, 2009Date of Patent: March 13, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20120058584Abstract: A light source and method for making the same are disclosed. The light source includes a substrate and a light emitting structure that is deposited on the substrate. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first segment in series with the second segment. A first blocking diode between the light emitting structure and the substrate prevents current from flowing between the light emitting structure and the substrate when the light emitting structure is emitting light. The barrier extends through the light emitting structure into the first blocking diode.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Inventors: Ghulam Hasnain, Steven D. Lester, Syn-Yem Hu, Jeff Ramer
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Patent number: 8129207Abstract: Disclosed are a light emitting diode having a thermal conductive substrate and a method of fabricating the same. The light emitting diode includes a thermal conductive insulating substrate. A plurality of metal patterns are spaced apart from one another on the insulating substrate, and light emitting cells are located in regions on the respective metal patterns. Each of the light emitting cells includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer. Meanwhile, metal wires electrically connect upper surfaces of the light emitting cells to adjacent metal patterns. Accordingly, since the light emitting cells are operated on the thermal conductive substrate, a heat dissipation property of the light emitting diode can be improved.Type: GrantFiled: September 16, 2011Date of Patent: March 6, 2012Assignee: Seoul Opto Device Co., Ltd.Inventor: Jae-Ho Lee
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Patent number: 8124433Abstract: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from the semiconductor material back into the semiconductor so as to enhance the likelihood of the light ultimately being transmitted from the semiconductor material. Such LED can have enhanced utility and can be suitable for uses such as general illumination.Type: GrantFiled: February 4, 2010Date of Patent: February 28, 2012Assignee: Bridgelux, Inc.Inventors: Frank T. Shum, William W. So, Steven B. Lester
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Patent number: 8114691Abstract: A semiconductor light emitting diode having a textured structure and a method of manufacturing the same are provided. The semiconductor light emitting diode includes a first semiconductor layer formed into a textured structure, an intermediate layer formed between the textured structures of the patterned first semiconductor layer, and a second semiconductor layer, an active layer, and a third semiconductor layer sequentially formed on the first semiconductor layer and the intermediate layer.Type: GrantFiled: December 4, 2009Date of Patent: February 14, 2012Assignee: Samsung LED Co., Ltd.Inventors: Jeong-wook Lee, Youn-joon Sung, Ho-sun Paek
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Patent number: 8114690Abstract: Aspects concerning a method of making electrical contact to a region of semiconductor in which one or more LEDs are formed include that a dielectric region can be formed on a p region of the semiconductor, and that a metallic electrode can be formed on (at least partially on) the region of dielectric material. A transparent layer of a material such as Indium Tin Oxide can be used to make ohmic contact between the semiconductor and the metallic electrode, as the metallic electrode is separated from physical contact with the semiconductor by one or more of the dielectric material and the transparent ohmic contact layer (e.g., ITO layer). The dielectric material can enhance total internal reflection of light and reduce an amount of light that is absorbed by the metallic electrode.Type: GrantFiled: September 22, 2010Date of Patent: February 14, 2012Assignee: Bridgelux, Inc.Inventors: Frank T. Shum, William W. So, Steven D. Lester
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Patent number: 8115224Abstract: A light emitting device That includes a first photonic crystal structure having a reflective layer and non-metal pattern elements on the reflective layer, a second conductive semiconductor layer on both the reflective layer and the non-metal pattern elements, an active layer on the second conductive semiconductor layer, and a first conductive semiconductor layer on the active layer.Type: GrantFiled: October 5, 2009Date of Patent: February 14, 2012Assignee: LG Innotek Co., Ltd.Inventor: Sun Kyung Kim
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Patent number: 8115226Abstract: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an dielectric material formed intermediate the electrode and a light emitting semiconductor material. Electrical continuity between the semiconductor material and the metal electrode is provided by an optically transmissive ohmic contact layer, such as a layer of Indium Tin Oxide. The metal electrode thus can be physically separated from the semiconductor material by one or more of the dielectric material and the ohmic contact layer. The dielectric layer can increase total internal reflection of light at the interface between the semiconductor and the dielectric layer, which can reduce absorption of light by the electrode. Such LED can have enhanced utility and can be suitable for uses such as general illumination.Type: GrantFiled: September 22, 2010Date of Patent: February 14, 2012Assignee: Bridgelux, Inc.Inventors: Frank T. Shum, William W. So, Steven D. Lester
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Publication number: 20120018763Abstract: A radiation-emitting semiconductor chip includes: a carrier and a semiconductor body with a semiconductor layer sequence including an active region that generates radiation, a first semiconductor layer and a second semiconductor layer; wherein the active region is arranged between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is arranged on a side of the active region which faces away from the carrier; the semiconductor body comprises at least one recess which extends through the active region; the first semiconductor layer is electrically conductively connected to a first connection layer extending in the recess from the first semiconductor layer in a direction of the carrier; and the first connection layer is electrically connected to the second semiconductor layer via a protective diode.Type: ApplicationFiled: June 25, 2009Publication date: January 26, 2012Applicant: OSRAM Opto Semiconductors GmbHInventors: Karl Engl, Berthold Hahn, Klaus Streubel, Markus Klein
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Patent number: 8101447Abstract: The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.Type: GrantFiled: December 20, 2007Date of Patent: January 24, 2012Assignee: Tekcore Co., Ltd.Inventors: Hung-Cheng Lin, Chia-Ming Lee, Jen-Inn Chyi
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Patent number: 8093081Abstract: A device of a light-emitting diode and a method for fabricating the same are provided. The LED device is made by forming a patterned epitaxial layer, a light-emitting structure, etc., on a substrate. In a subsequent process, the patterned epitaxial layer serves as a weakened structure, and can be automatically broken and a rough surface is thus formed. The weakened structure is formed with a specified height, and has pillar structures. The light-emitting structure is formed on the weakened structure. During a cooling process at room temperature, the weakened structure is automatically broken and a rough surface is thus formed.Type: GrantFiled: September 18, 2009Date of Patent: January 10, 2012Assignee: Industrial Technology Research InstituteInventors: Po-Chun Liu, Chu-Li Chao, Yih-Der Guo
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Patent number: 8093077Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C.Type: GrantFiled: March 11, 2009Date of Patent: January 10, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Hacene Lahreche
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Patent number: 8093085Abstract: A method of forming a suspension object on a monolithic substrate is provided. A silicon base layer of the monolithic substrate has a circuit layer composed of at least one wet etching region, at least one circuit region, and at least one microstructure region. The wet etching region is used to partition the circuit region and the microstructure region, and extends downwards to a surface of the silicon base layer, so as to form an etching path for etching the silicon base layer from above the substrate. Next, an upper surface and a lower surface of the silicon base layer are respectively etched through dry etching, such that the microstructure region is suspended.Type: GrantFiled: June 15, 2010Date of Patent: January 10, 2012Assignee: Memsor CorporationInventor: Siew Seong Tan
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Patent number: 8090229Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.Type: GrantFiled: April 22, 2011Date of Patent: January 3, 2012Assignee: QUALCOMM MEMS Technologies, Inc.Inventor: Karen Tyger
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Patent number: 8089091Abstract: A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure includes an n-contact region and a p-contact region. A cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and p-type region are removed to expose the n-type region. The plurality of first regions are separated by a plurality of second regions wherein the light emitting layer and p-type region remain in the device. The device further includes a first metal contact formed over the semiconductor structure in the p-contact region and a second metal contact formed over the semiconductor structure in the n-contact region. The second metal contact is in electrical contact with at least one of the second regions in the n-contact region.Type: GrantFiled: June 18, 2009Date of Patent: January 3, 2012Assignee: Koninklijke Philips Electronics N.V.Inventor: John E. Epler
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Patent number: 8076675Abstract: An LED chip includes a substrate and a p-n junction type semiconductor light-emitting structure. The substrate has a first surface and a second surface opposite to the second surface. The p-n junction type semiconductor light-emitting structure is arranged on the first surface of the substrate. A plurality of blind holes is defined in the second surface of the substrate and extends from the second surface towards the first surface. A heat conductive material is filled in each of the plurality of blind holes thereby forming a plurality of heat conductive poles in the plurality of blind holes.Type: GrantFiled: December 30, 2009Date of Patent: December 13, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Da-Wei Lin
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Patent number: 8076167Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.Type: GrantFiled: July 14, 2010Date of Patent: December 13, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Patent number: 8071442Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.Type: GrantFiled: September 2, 2009Date of Patent: December 6, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Andreas Ott
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Patent number: 8071405Abstract: Provided is a group-III nitride semiconductor laser device with a laser cavity enabling a low threshold current, on a semipolar surface of a support base the c-axis of a hexagonal group-III nitride of which tilts toward the m-axis. In a laser structure 13, a first surface 13a is a surface opposite to a second surface 13b and first and second fractured faces 27, 29 extend each from an edge 13c of the first surface 13a to an edge 13d of the second surface 13b. A scribed mark SM1 extending from the edge 13c to the edge 13d is made, for example, at one end of the first fractured face 27, and the scribed mark SM1 or the like has a depressed shape extending from the edge 13c to the edge 13d. The fractured faces 27, 29 are not formed by dry etching and thus are different from the conventional cleaved facets such as c-planes, m-planes, or a-planes. It is feasible to use emission of a band transition enabling a low threshold current.Type: GrantFiled: July 14, 2010Date of Patent: December 6, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Patent number: 8067300Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: April 28, 2009Date of Patent: November 29, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Patent number: 8058082Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.Type: GrantFiled: August 11, 2008Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu, Hung-Ta Lin
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Patent number: 8053262Abstract: A method for manufacturing a nitride semiconductor laser element having a nitride semiconductor layer including at least an active layer provided on a substrate, a pair of cavity planes formed on the nitride semiconductor layer, and a protruding part where part of the substrate protrudes from said cavity plane, said method comprises: a step of forming the nitride semiconductor layer on the substrate; a first etching step of forming a first groove by etching at least the nitride semiconductor layer; and a second etching step of forming the cavity plane, in the second etching step, the inner wall of the first groove and part of the nitride semiconductor layer surface adjacent to the first groove are etched to form a second groove, and form the upper face of the protruding part.Type: GrantFiled: April 28, 2009Date of Patent: November 8, 2011Assignee: Nichia CorporationInventor: Shingo Tanisaka
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Patent number: 8049233Abstract: A light-emitting device of the present invention includes: a semiconductor layer 1 including a light-emitting layer 12; a recess/projection portion 14 including recesses and projections formed in a pitch larger than a wavelength of light emitted from the light-emitting layer 12, the recess/projection portion 14 being formed in a whole area or a partial area of the surface of the semiconductor layer which light is emitted from; and a reflective layer formed on an opposite surface of the semiconductor layer to the surface from which light is emitted, the reflective layer having a reflectance of 90% or more. According to the light-emitting device having such arrangement, the light can be emitted efficiently by synergetic effect of the reflective layer and the recess/projection portion.Type: GrantFiled: March 9, 2007Date of Patent: November 1, 2011Assignee: Panasonic Electric Works Co., Ltd.Inventors: Hiroshi Fukshima, Masaharu Yasuda, Kazuyuki Yamae
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Publication number: 20110255294Abstract: A semiconductor light-emitting device (1) of the present invention includes: a substrate (101); a laminated semiconductor layer (20) containing a light-emitting layer, which is formed on the substrate (101); a first electrode (111) formed on the upper surface (106c) of the laminated semiconductor layer (20); and a second electrode (108) formed on an exposed surface (104c) that is formed by partially cutting the laminated semiconductor layer (20), wherein the first electrode (111) includes a transparent electrode (109) containing a hole portion (109a) through which the upper surface (106c) of the laminated semiconductor layer (20) is exposed, a junction layer (110) formed on a bottom surface (109b) and an inner wall (109d) of the hole portion (109a), and a bonding pad electrode (120) formed to cover the junction layer (110).Type: ApplicationFiled: December 15, 2009Publication date: October 20, 2011Applicant: SHOWA DENKO K.K.Inventors: Takehiko Okabe, Daisuke Hiraiwa, Remi Ohba
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Publication number: 20110254044Abstract: A light emitting device and a method of fabricating a light emitting device are provided. The light emitting device includes a carrier substrate, at least one epitaxy structure, a high resistant ring wall, a first electrode, and a second electrode. The epitaxy structure is disposed on the carrier substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is relatively away from the carrier substrate and the second semiconductor layer is relatively close to the carrier substrate. The high resistant ring wall surrounds the epitaxy structure and a width of the high resistant ring wall is greater than 5 ?m. The first electrode is disposed between the carrier substrate and the epitaxy structure. The second electrode is disposed at a side of the epitaxy structure away from the carrier substrate.Type: ApplicationFiled: March 24, 2011Publication date: October 20, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wei-Hung Kuo, Yi-Keng Fu, Suh-Fang Lin, Rong Xuan
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Patent number: 8039864Abstract: A high luminance semiconductor light emitting device and a fabrication method for such semiconductor light emitting device are provided by forming a metallic reflecting layer using a non-transparent semiconductor substrate.Type: GrantFiled: June 6, 2008Date of Patent: October 18, 2011Assignee: Rohm Co., Ltd.Inventors: Masakazu Takao, Mitsuhiko Sakai, Shunji Nakata
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Patent number: 8038890Abstract: A piezoelectric-driven MEMS device can be fabricated reliably and consistently. The piezoelectric-driven MEMS device includes: a movable flat beam having a piezoelectric film disposed above a substrate with a recessed portion such that the piezoelectric film is bridged over the recessed portion, piezoelectric drive mechanisms disposed at both ends of the piezoelectric film and configured to drive the piezoelectric film, and a first electrode disposed at the center of the substrate-side of the piezoelectric film, and a second electrode disposed on a flat part of the recessed portion of the substrate and facing the first electrode of the movable flat beam.Type: GrantFiled: February 27, 2008Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawakubo, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki
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Patent number: 8030110Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.Type: GrantFiled: December 27, 2010Date of Patent: October 4, 2011Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki, Yoshika Kaneko
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Patent number: 8030108Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.Type: GrantFiled: June 26, 2009Date of Patent: October 4, 2011Assignee: STC.UNMInventors: Seung Chang Lee, Steven R. J. Brueck
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Patent number: 8030104Abstract: A method for manufacturing a liquid crystal display device is disclosed.Type: GrantFiled: August 21, 2008Date of Patent: October 4, 2011Assignee: LG Display Co., Ltd.Inventors: Sung Il Park, Dae Lim Park
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Patent number: 8026156Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.Type: GrantFiled: June 23, 2009Date of Patent: September 27, 2011Assignee: Samsung LED Co., Ltd.Inventors: Soo Min Lee, Cheol Kyu Kim, Jaeun Yoo, Sung Hwan Jang, Masayoshi Koike
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Patent number: 8021943Abstract: A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.Type: GrantFiled: November 25, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Alan B. Botula, BethAnn Rainey, Daniel S. Vanslette
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Patent number: 8017423Abstract: The present invention discloses a method for manufacturing thin film structure, which comprises the following steps: providing a substrate having a first recess and a second recess formed therein with the first recess being deeper than the second recess; depositing a first material layer and a second material layer of different thicknesses successively on the substrate; and grinding the substrate so that a flat upper surface is formed and the first material layer and the second material layer are remained in the first recess while only the first material layer is remained in the second recess. The present invention also discloses a method for manufacturing fringe field switching type liquid crystal display array substrate. With the present invention, it is possible to make the upper surface flat while forming patterns on two layers of thin films respectively by using a single mask.Type: GrantFiled: September 17, 2009Date of Patent: September 13, 2011Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Seongyeol Yoo, Youngsuk Song, Seungjin Choi
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Patent number: 8017962Abstract: A light-emitting diode (LED) apparatus includes a thermoconductive substrate, a thermoconductive adhesive layer, an epitaxial layer, a current spreading layer and a micro- or nano-roughing structure. The thermoconductive adhesive layer is disposed on the thermoconductive substrate. The epitaxial layer is disposed opposite to the thermoconductive adhesive layer and has a first semiconductor layer, an active layer and a second semiconductor layer. The current spreading layer is disposed between the second semiconductor layer of the epitaxial layer and the thermoconductive adhesive layer. The micro- or nano-roughing structure is disposed on the first semiconductor layer of the epitaxial layer. In addition, a manufacturing method of the LED apparatus is also disclosed.Type: GrantFiled: August 18, 2008Date of Patent: September 13, 2011Assignees: Delta Electronics, Inc., National Central UniversityInventors: Shih-Peng Chen, Chia-Hua Chan, Horng-Jou Wang, Ching-Liang Lin, Chii-Chang Chen, Cheng-Yi Liu, Huang-Kun Chen
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Patent number: 8017497Abstract: A method for manufacturing a high quality semiconductor device having a through via structure. A substrate is manufactured with an oxide layer including a window region in a region in which a through via is formed. The substrate is bonded with another substrate to form an SOI substrate. The SOI substrate is ground to reduce its thickness. An island region is formed in a region at which a TSV (Through Silicon Via) structure is formed. A device and a TSV are coupled by a wire. The silicon substrate at a bottom side of the SOI substrate is removed to expose the island region from the bottom. A back contact for the TSV is formed in the window region, which is formed in a buried oxide layer.Type: GrantFiled: January 14, 2010Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventor: Hideo Oi
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Patent number: 8017420Abstract: Provided is a method of forming optical waveguide. The method includes forming a trench on a semiconductor substrate to define an active portion, and partially oxidizing the active portion. An non-oxidized portion of the active portion is included in a core through which an optical signal passes, and an oxidized portion of the active portion is included in a cladding.Type: GrantFiled: June 25, 2009Date of Patent: September 13, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: In-Gyoo Kim, Dong-Woo Suh, Gyung-Ock Kim
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Patent number: 8008103Abstract: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.Type: GrantFiled: December 14, 2009Date of Patent: August 30, 2011Assignees: LG Innotek Co., Ltd., LG Electronics Inc.Inventors: Hyun Kyong Cho, Sun Kyung Kim, Jun Ho Jang
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Patent number: 8003418Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor light-emitting device, wherein a contact electrode is formed on an N-polar surface of an n-type layer through annealing at 350° C. or lower. In the case where, in a Group III nitride-based compound semiconductor device produced by the laser lift-off process, a contact electrode is formed, through annealing at 350° C. or lower, on a micro embossment surface (i.e., a processed N-polar surface) of an n-type layer from vanadium, chromium, tungsten, nickel, platinum, niobium, or iron, when a pseudo-silicon-heavily-doped layer is formed on the micro embossment surface (i.e., N-polar surface) of the n-type layer through treatment with a plasma of a silicon-containing compound gas, and treatment with a fluoride-ion-containing chemical is not carried out, ohmic contact is obtained, and low resistance is attained.Type: GrantFiled: March 30, 2010Date of Patent: August 23, 2011Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Umemura, Ryohei Inazawa, Koichi Goshonoo, Tomoharu Shiraki
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Publication number: 20110198609Abstract: Multiple through-substrate vias (TSVs) are used to make electrical connections for an LED formed over a substrate. A first TSV extends through the substrate from a back surface of the substrate to the front surface of the substrate and includes a first TSV conductor that electrically connects to a first cladding layer of the LED. A second TSV extends through the substrate and an active layer of the LED from the back surface of the substrate to a second cladding layer or an ITO layer. The second TSV includes an isolation layer that electrically isolates a second TSV conductor from the first cladding layer and the active layer. Additionally dummy TSVs may be formed to conduct heat away from the LED optionally through a package substrate.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsin-Chieh Huang
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Patent number: 7998772Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.Type: GrantFiled: December 3, 2009Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
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Patent number: 7998771Abstract: Provided is a method of manufacturing a light emitting diode using a nitride semiconductor, which including the steps of: forming n- and p-type current spreading layers using a hetero-junction structure; forming trenches by dry-etching the n- and p-type current spreading layers; forming an n-type metal electrode layer in the trench of the n-type current spreading layer; forming a p-type metal electrode layer in the trench of the p-type current spreading layer; and forming a transparent electrode layer on the p-type metal electrode layer, thereby improving current spreading characteristics as compared with the conventional method of manufacturing the light emitting diode, and enhancing operating characteristics of the light emitting diode.Type: GrantFiled: November 26, 2007Date of Patent: August 16, 2011Assignee: Electronics and Telecommunications Research InstituteInventor: Sung Bum Bae
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Patent number: 7989238Abstract: Provided is a Group III nitride-based compound semiconductor light-emitting device including aluminum regions. The Group III nitride-based compound semiconductor light-emitting device includes a sapphire substrate; aluminum regions which are formed on the substrate; an AlN buffer layer; an Si-doped GaN n-contact layer; an n-cladding layer formed of multiple layer units, each including an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer; an MQW light-emitting layer including alternately stacked eight well layers formed of In0.2Ga0.8N and eight barrier layers formed of GaN and Al0.06Ga0.94N; a p-cladding layer formed of multiple layers including a p-type Al0.3Ga0.7N layer and a p-type In0.08Ga0.92N layer; a p-contact layer having a layered structure including two p-type GaN layers having different magnesium concentrations; and an ITO light-transmitting electrode.Type: GrantFiled: June 10, 2009Date of Patent: August 2, 2011Assignee: Toyoda Gosei Co., Ltd.Inventor: Koji Okuno