Abstract: An extreme ultraviolet (EUV) collector inspection apparatus and method capable of precisely inspecting a contamination state of an EUV collector and EUV reflectance in accordance with the contamination state are provided. The EUV collector inspection apparatus includes a light source arranged in front of an EUV collector to be inspected and configured to output light in a visible light (VIS) band from UV rays, an optical device configured to output narrowband light from the light, and a camera configured to perform imaging from an UV band to a VIS band. An image by wavelength of the EUV collector is obtained by using the optical device and the camera and a contamination state of the EUV collector is inspected.

Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of pillars on a substrate. Each pillar of the plurality of pillars includes a silicon germanium portion. In the method, a layer of germanium oxide is deposited on the plurality of pillars, and a thermal annealing process is performed to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes. Each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion. The method also includes exposing top surfaces of each of the silicon germanium core portions, and selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

Abstract: A method is provided, including successive steps of a) providing a donor substrate covered with a layer of oxide; b) implanting gaseous species in the donor substrate, through the layer to form an embrittlement zone, and at the end of step b), the layer has an absorbance peak with a maximum at a first wavenumber, and with a full width at half maximum; c) applying ultraviolet radiation to the free surface of the layer under an ozone atmosphere and according to a thermal budget for: shifting the maximum by at least 3 cm?1 towards increasing wavenumbers, reducing the full width at half maximum by at least 3 cm?1, and allowing direct adhesion with the free surface; d) assembling the donor substrate on the supporting substrate by direct adhesion with the free surface; and e) splitting the donor substrate along the embrittlement zone to expose a useful layer.

Abstract: This method comprises the successive steps of providing a donor substrate comprising a first surface; smoothing the first surface of the donor substrate until a reconstructed surface topology is obtained; forming a first dielectric film on the smoothed first surface of the donor substrate, in such a way that the first dielectric film has a surface that preserves the reconstructed surface topology; implanting gaseous species in the donor substrate, through the first dielectric film, so as to form an embrittlement zone, the useful layer being delimited by the embrittlement zone and by the first surface of the donor substrate; assembling the donor substrate on the supporting substrate by direct adhesion; and splitting the donor substrate along the embrittlement zone so as to expose the useful layer.

Abstract: A method for manufacturing a resistivity standard sample include the steps, preparing a first-conductivity-type silicon single crystal substrate, measuring a thickness of the silicon single crystal substrate by using a thickness measuring instrument having traceability to the national standard, growing a second-conductivity-type silicon epitaxial layer on the silicon single crystal substrate to fabricate an epitaxial wafer having a p-n junction, measuring a thickness of the epitaxial wafer by using the thickness measuring instrument having the traceability to the national standard, obtaining a thickness of the silicon epitaxial layer from the thicknesses of the epitaxial wafer and the silicon single crystal substrate, and measuring a resistivity of the silicon epitaxial layer by using a resistivity measuring instrument having traceability to a resistivity standard reference material.

Abstract: The invention relates to methods and an apparatus for passivating defects of a semiconductor substrate, in particular a silicon based solar cell. According to the method, the substrate is irradiated with electromagnetic radiation during a first process phase, wherein the radiation directed onto the substrate has wavelengths at least in the region below 1200 nm and an intensity of at least 8000 Watt/m2. This can lead to a heating of the substrate, or a temperature control can be provided. Subsequently, the substrate is irradiated with electromagnetic radiation during a temperature-holding phase following the first process phase, wherein the radiation directed onto the substrate has wavelengths primarily in the region below 1200 nm and an intensity of at least 8000 Watt/m2, while a side of the substrate facing away from a source of the electromagnetic radiation is cooled via a contact with a support cooled by a cooling device.

Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.

Abstract: Some embodiments of the present disclosure related to a method to form and operate the reflective surface to compensate for aberration effects on pattern uniformity. In some embodiments, the reflective surface comprises a mirror of within reduction optics of an EUV illumination tool. In some embodiments, the reflective surface comprises a reflective reticle. An EUV reflective surface topography comprising a reflective surface is disposed on a surface of a substrate, and is manipulated by mechanical force or thermal deformation. The substrate includes a plurality of cavities, where each cavity is coupled to a deformation element configured to expand a volume of the cavity and consequently deform a portion of the reflective surface above each cavity, for local control of the reflective surface through thermal deformation of a resistive material subject to an electric current, or mechanical deformation due to pressurized gas within the cavity or a piezoelectric effect.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thic

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.

Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.

Abstract: A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*1014 cm?3, and partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface. Further, a semiconductor device is provided.

Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract: A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the first-type doped layer and the second-type doped layer.

Abstract: The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess.

Abstract: A method for mechanically separating a laminar structure from a first carrier assembly, comprising or consisting of a first carrier, wherein the laminar structure comprises a wafer and a second, stretchable carrier is disclosed. Also disclosed are the use of a particular separating aid for separating a laminar structure and a device for carrying out the method.

Abstract: The present invention includes: a silicon-based substrate; and an epitaxial growth layer that has a configuration in which first and second nitride semiconductor layers having different lattice constants and thermal expansion coefficients are alternately laminated, and is arranged on the silicon-based substrate so that a film thickness thereof is gradually reduced at an outer edge portion. As a result, there are provided an epitaxial substrate and a semiconductor device in which generation of cracks at the outer edge portion is suppressed, and a method for manufacturing the semiconductor device.

Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.

Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.

Abstract: The embodiments described herein generally relate to methods for forming a multi-layer amorphous silicon structure that may be used in thin film transistor devices. In one embodiment, a method includes positioning a substrate comprising a buffer layer in a process chamber, the process chamber comprising a processing region, forming a plurality of amorphous silicon layers and annealing the amorphous silicon layers to form a polycrystalline silicon layer. Forming the plurality of layers includes delivering a silicon-containing precursor and a first activation gas to the processing region to deposit a first amorphous silicon layer over the buffer layer, the silicon-containing precursor and the first activation gas being activated by a plasma and maintaining a continuous flow of the silicon-containing precursor while delivering a second activation gas, without the first activation gas, to the processing region to deposit a second silicon layer on the first silicon layer.

Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.

Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.

Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.

Abstract: A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*1014 cm?3, and partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface. Further, a semiconductor device is provided.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.

Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.

Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.

Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect.

Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.

Abstract: A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and carbon atoms as an impurity are present at not less than 3 at % and not more than 25 at %. Thereby, a silicon carbide substrate having a stable surface, a semiconductor device using the substrate, and methods for manufacturing them can be provided.

Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.

Abstract: The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.

Abstract: There is provided a semiconductor substrate for solid-state image sensing device in which the production cost is lower than that of a gettering method through a carbon ion implantation and problems such as occurrence of particles at a device production step and the like are solved. Silicon substrate contains solid-soluted carbon having a concentration of 1×1016-1×1017 atoms/cm3 and solid-soluted oxygen having a concentration of 1.4×1018-1.6×1018 atoms/cm3.

Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

Abstract: An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step.

Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.