Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.

Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.

Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer contains hydrogen mostly in form of hydrogen platelets oriented in parallel to each other and to neighboring crystal surface. The fragile layer is preferably grown within a single crystalline silicon wafer to facilitate the detachment of an overlaying thin layer of single crystalline silicon from the initial wafer. The hydrogen layer is grown on a seed layer. The seed layer is preferably formed by ion implantation of inert gases at doses in 1015 cm?2 range. The hydrogen layer is grown by plasma hydrogenation of the substrate. The hydrogenation process begins at substrate temperature not exceeding 250° C., and than continues at higher temperature not exceeding 400° C.

Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.

Abstract: The invention provides a method of reducing the roughness of the free surface of a wafer of semiconductor material by applying a rapid thermal annealing process under a pure argon atmosphere for a time sufficient to uniformly heat and smooth the free surface of the wafer.

Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites.

Abstract: Methods for forming a single crystal semiconductor thin film layer from a non-single crystal layer includes directing a light source having a homogenized intensity distribution and a modulated amplitude towards the non-single crystal layer, and relatively moving the light with respect to the layer wherein the amplitude of the conditioned light is preferably increased in the direction of relative motion of the light to the layer. Preferred methods also include multiple light exposures in overlapping series to form ribbon-shaped single crystal regions, and providing a low temperature point in the semiconductor layer to generate a starting location for single crystalization.

Abstract: One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

Abstract: The present invention provides a manufacturing method of a semiconductor device, which is able to improve on-current and mobility of a polycrystal TFT without disturbing a high integration level, and also provide a semiconductor device obtained in accordance with the manufacturing method.

Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial oxidation stage for removing material constituting the working layer (6) over a certain surface thickness of each substrate (1), a stage of polishing (200) the face which has been subjected to the first sacrificial oxidation stage (100), and a second sacrificial oxidation stage for again removing material constituting the working layer (6) on the polished face (17).

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: A getter device is shaped like a substrate used in a deposition process. Embodiments of the device include a powdered getter material coated onto one or both sides of a support with a narrow rim portion left uncoated so that the device can be manipulated by automatic handling equipment. A method for using the getter device includes providing a vacuum chamber and automatic handling equipment, loading the device into the chamber, reducing the chamber pressure to a desired value by using the getter device in conjunction with an external pump, removing the getter device and replacing it with a substrate, and depositing a thin film on the substrate. The getter device can be in an activated state when loaded into the chamber, or it can be activated after being loaded by employing heating equipment ordinarily used to heat substrates placed in the chamber. The getter material of the device may also be activated in a separate activation chamber before the getter device is loaded into the vacuum chamber.

Abstract: A single substrate hydrogen and microwave absorber (20) attenuates spurious microwave signals in a metal Integrated Microwave Assembly (10, 10?) and reduces hydrogen poisoning of hydrogen sensitive components implemented in the Integrated Microwave Assembly (10, 10?). The single substrate hydrogen and microwave absorber (20) includes a titanium substrate (30) with channels (32) spaced apart from one another by a predetermined distance. A layer of microwave absorbing material (34) is formed on portions (35) of the titanium substrate (30) between the channels (32), and a layer of hydrogen getting material (36) is formed in the channels (32) of the titanium substrate (30).

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: An in-line chemical feed pump for a foam dispenser system that has an inlet conduit for receiving chemical fluid, a pump head in chemical fluid communication with the inlet conduit, an outlet conduit in chemical fluid communication with the pump head, and a driver. In addition, there is provided a pump drive transmission system positioned in drive transmission communication between the driver and pump head, with the pump drive transmission system including a magnetic coupling with first and second magnetic coupling members placed to opposite sides of an intermediate protective shroud, and with the shroud having a coupling reception cavity which receives one of said first and second magnetic coupling members. A method of dispensing foam using an in-line chemical feed pump is also featured including use of a system where two chemical lines are involved each with the in-line pump assembly and each line feeding to a mixing module of a dispenser.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: A mask including a material, which has heat resistance and light absorptivity, is selectively formed on a crystalline silicon film containing a catalytic element. Next, by using the mask, phosphorus is implanted into the silicon film and an implanted portion of the silicon film is transformed into amorphous. Then the silicon film is heated by a rapid thermal annealing (RTA) method, so that the temperature of the portion covered with the mask becomes higher than other portions. As a result, the catalytic element moves from the high temperature portion covered with the mask to the lower temperature amorphous portion in which phosphorus has been implanted and which has a large gettering capacity. Thus, the concentration of the catalytic element in the portion covered with the mask is lowered, and a semiconductor device is manufactured by using the film.

Abstract: Disclosed are a non-volatile memory device to protect a floating gate from charge loss and a method for forming the same. At least a pair of floating gate lines are formed on a semiconductor substrate. A portion of the substrate between the floating gate lines is etched to form a trench therein. A gap-fill dielectric layer is formed in the trench and also in the gap between the pair of floating gate lines. The gap-fill dielectric layer is implanted with impurities so that positive mobile ions that may permeate the floating gate through the gap-fill dielectric layer can be trapped in the gap-fill dielectric layer.

Abstract: The invention relates to a method for generating defect profiles in a crystal or crystalline structure of a substrate, preferably a semiconductor, during a thermal treatment in a process chamber. According to the inventive method, a concentration and/or a density distribution of defects is controlled with at least one reactive component each depending on at least two process gases that differ in their composition. At least two of the process gases independently act upon at least two different surfaces of the substrate.

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality [ Oi ] < [ Oi ] eq ⁢ ( T ) ⁢ exp ⁢ ( 2 ⁢ σ SiO 2 ⁢ Ω rkT ) is satisfied, where [Oi] is the oxygen concentration in the silicon wafer [Oi]eq(T) is the limit solubility of oxygen in silicon at a temperature T, &sgr;SiO2 is the surface energy of silicon dioxide &OHgr; is the volum

Abstract: The method for fabricating a semiconductor device including a step of forming a gate insulation film on a semiconductor substrate 10, the method further comprises, before the step of forming the gate insulation film, the step of forming an insulation film 12, covering a first side (upper side) and a second side (underside) of the semiconductor substrate 10, the step of etching off the insulation film 12 on the first side of the semiconductor substrate 10, and the step of annealing the semiconductor substrate 10 with the insulation film 12 present on the second side of the semiconductor substrate 10.

Abstract: A method for reducing occurrences of loose gettering material particles within micro-electromechanical system (MEMS) devices is described. The MEMS devices include a micro-machine within a substantially sealed cavity formed by a housing and a cover for the housing. The cavity containing a getter mounted on a getter substrate which is to be attached to the cover. The method includes providing an area between a portion of the cover and a portion of the getter substrate, positioning the getter within the area, and attaching the getter substrate to the cover.

Abstract: The present invention provides an epitaxial wafer wherein a silicon epitaxial layer is formed on a surface of a silicon single crystal wafer in which nitrogen is doped, and a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk is 108 numbers/cm3 or more. And the present invention also provides a method for producing an epitaxial wafer wherein a silicon single crystal in which nitrogen is doped is pulled by Czochralski method, the silicon single crystal is processed into a wafer to produce a silicon single crystal wafer, and the silicon single crystal wafer is subjected to heat treatment so that a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk of the wafer may be 108 numbers/cm3 or more, and then the silicon single crystal wafer is subjected to epitaxial growth. A silicon single crystal wafer which surely has a high gettering capability irrespective of a device process can be obtained herewith.

Abstract: There is provided a method for manufacturing a silicon wafer or a silicon epitaxial wafer capable of imparting an excellent IG capability thereto in a stable manner by simultaneously realizing higher density of oxide precipitates and larger sizes thereof at a stage prior to a device fabrication process. The present invention is a method for manufacturing a silicon wafer wherein the silicon wafer is subjected to heat treatment to impart a gettering capability thereto comprising at least the following three steps of: a temperature raising step A for generating oxygen precipitation nuclei; a temperature raising step B for growing the oxygen precipitation nuclei; and a constant temperature keeping step C for growing the oxygen precipitation nuclei into oxide precipitates of larger sizes.

Abstract: Provided are a semiconductor and semiconductor substrate exhibiting low resistance on the substrate side while exhibiting high resistivity in an epitaxially grown layer formed thereover; a method of manufacturing the same; and a semiconductor device employing this semiconductor. The semiconductor consists of a compound single crystal and comprises a region having a planar defect density of 1×107/cm2 or more and a region having a planar defect density of 1/cm2 or less. The semiconductor substrate comprises the aforementioned semiconductor on a substrate. The methods of manufacturing the aforementioned semiconductor and semiconductor substrate are also provided.

Abstract: A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an amorphous silicon film 203, a head treatment is carried out to thereby crystallize the amorphous silicon film. Further, by carrying out a heat treatment in an oxidizing atmosphere containing a halogen element, a thermal oxidation film 209 is formed. At this time, cyrstallinity is improved and gettering of the nickel element proceeds. TFTs are formed by using the thus obtained crystalline silicon film, and various circuits are constituted by using the TFTs, so that a data driver circuit capable of driving the active matrix circuit having the dot number of fifty thousands to three millions can be obtained.

Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.

Abstract: Disclosed is a method of manufacturing the semiconductor devices. The method comprising the steps of forming a gate electrode on a semiconductor substrate, depositing an oxide film for a spacer on the gate electrode, implementing an anisotropic dry etch process for the oxide film for the spacer to form spacers at the sidewalls of the gate electrode, and implementing a rapid thermal annealing process for the spacers under an oxygen atmosphere in order to segregate hydrogen contained within the spacers toward the surface. Therefore, hydrogen contained within the spacer oxide film is not diffused into the tunnel oxide film and the film quality of the tunnel oxide film is thus improved. As a result, program or erase operation characteristics of the flash memory device and a retention characteristic of the flash memory device could be improved.

Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.

Abstract: A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer.

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: There are provided a heat-treating method capable of both increasing BMD density and widening DZ layer width, and a silicon wafer having DZ layer width wider compared with a conventional one regardless of high BMD density. In the method, heat treatment (RTA treatment) is performed to a silicon wafer containing interstitial oxygen with a rapid heating-rapid cooling apparatus, thereby atomic vacancies being injected from a surface of the wafer to form a maximum position of an atomic vacancy concentration in a depth direction in the vicinity of the surface of the wafer, and thereafter heat treatment (post annealing) is performed to move the maximum position of the atomic vacancy concentration in the vicinity of the surface of the wafer into the inside of the wafer.

Abstract: The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is less susceptible to performance degradation caused by hydrogen contamination. The method includes the steps for removing unwanted hydrogen bonds by exposing the hydrogen bonds to ultraviolet radiation sufficient to break the bond and annealing in an atmosphere comprising at least one gas having at least one atom capable of forming bonds that replace the hydrogen bonds.

Abstract: A technique for forming a gettering layer in a wafer made using a controlled cleaving process. The gettering layer can be made by implanting using beam line or plasma immersion ion implantaion, or made by forming a film of material such as polysilicon by way of chemical vapor deposition. A controlled cleaving process is used to form the wafer, which is a multilayered silicon on insulator substrate. The gettering layer removes and/or attracts impurities in the wafer, which can be detrimental to the functionality and reliability of an integrated circuit device made on the wafer.

Abstract: A method of manufacturing a pressure sensor house assembly which contains a reference cavity, in which a vacuum exists, and a getter capable of being thermally activated. The getter is activated by directly contacting the getter with an exterior heated body, conducting heat from the exterior heated body, maintaining the exterior heated body in direct contact with the getter for a predetermined period of time, and removing the exterior heated body.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a bulk layer between front and back surface layers. The wafer is subjected to a heat-treatment in an atmosphere to form crystal lattice vacancies. A surface of the wafer is oxidized by heating in the presence of an oxygen-containing atmosphere to effect the vacancy concentration profile. The wafer is cooled at a rate which allows some, but not all, the crystal lattice vacancies to diffuse to the surfaces such that the concentration of vacancies in the bulk layer is greater than in the surface layers. The vacancy concentration profile shape is determined in part by the heat-treatment atmosphere, in part by the surface oxidation, and in part by the cooling rate.

Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.

Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or purifier material is deposited on the base by a variety of techniques and a layer for temporary protection of the purification material is placed on top of the purification material. The temporary protection material is compatible for use in the microdevice and can be removed during the manufacture of the microdevice.

Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.

Abstract: Disclosed is a method of manufacturing a semiconductor wafer. In the present invention, a nucleation site is formed in a region deep into the wafer through low-temperature annealing process, and oxygen or precipitation material, the metallic impurity, or the like is trapped in the nucleation site through rapid thermal annealing process. As a gettering effect is improved using the rapid thermal annealing process, the concentration of the impurity on the surface of the wafer can be lowered and the reliability of the device could be improved. Further, the annealing steps can be reduced than the prior art and the productivity of the device can thus be increased.

Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: A method for non-destructively evaluating the concentration of impurities in an epitaxial susceptor used in the processing of a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels on the epitaxial susceptor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A method of fabricating a silicon wafer, which includes the steps of preparing a silicon wafer by slicing, grinding, and cleaning an ingot, inserting the silicon wafer in a diffusion furnace having an ambience of one of Ar, N2 and inert gas including Ar and N2, pre-heating and maintaining the diffusion furnace at about 500° C., changing the ambience into one of H2, Ar and inert gas including H2 and Ar successively, increasing a temperature of the diffusion furnace by a temperature-increasing speed of 50˜70° C./min between 500˜800° C., 10˜50° C./min between 800˜900° C., 0.5˜10° C./min between 900˜1000° C., and 0.1˜0.5° C./min between 1000˜1250° C., maintaining the diffusion furnace at 1200˜1250° C.

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.