Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline semiconductor film. A semiconductor layer includes a region containing an impurity element which has a concentration of 1×1019/cm3 to 1×1021/cm3 and belongs to group 15 of the periodic table and an impurity element which has a concentration of 1.5×1019/cm3 to 3×1021/cm3 and belongs to group 13 of the periodic table, and the region is a region to which a catalytic element left in the semiconductor film (particularly, the channel forming region) moves.

Abstract: System and method for filling vias in integrated circuits A preferred embodiment comprises forming a spacer layer on a substrate, forming a via with walls and a bottom in the spacer layer, depositing a conformal conductive layer on the spacer layer and on the walls and bottom of the via, spinning-on a photo-definable material on the conductive layer, forming a fill layer on the conductive layer and filling the via, exposing portions of the fill layer to an exposing light using a photomask, developing the fill layer to remove select portions of the fill layer and leave a portion of the fill layer filling the via, and removing the spacer layer. The use of a spin-on photo-definable material increases the material's filling and planarizing capabilities, while enabling a reduction in the number of process steps, which may reduce the likelihood of manufacturing defects, thereby increasing manufacturing yield.

Abstract: In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.

Abstract: A multilayered substrate structure comprising one or more devices, e.g., optoelectronic, integrated circuit. The structure has a handle substrate, which is characterized by a predetermined thickness and a Young's modulus ranging from about 1 Mega Pascal to about 130 Giga Pascal. The structure also has a thickness of substantially crystalline material coupled to the handle substrate. Preferably, the thickness of substantially crystalline material ranges from about 100 microns to about 5 millimeters. The structure has a cleaved surface on the thickness of substantially crystalline material and a surface roughness characterizing the cleaved film of less than 200 Angstroms. At least one or more optoelectronic devices is provided on the thickness of material.

Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.

Abstract: A method for providing improved gettering in a vacuum encapsulated device is described. The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of the getter material, thereby increasing the volume of gas that the getter material can absorb. This may improve the vacuum maintained within the vacuum cavity over the lifetime of the vacuum encapsulated device.

Abstract: A method of surface treating a phase change layer may include, before forming the phase change layer, forming a coating layer on a surface of a bottom layer on which the phase change layer is to be formed, wherein the coating layer has a chemical structure for contributing to the adherence of an alkyl radical to the surface of the bottom layer. After forming the coating layer, the phase change layer may be formed using an atomic layer deposition (ALD) method.

Abstract: A method of subjecting a silicon wafer doped with boron to a heat treatment in an argon atmosphere, wherein the argon atmosphere is replaced with a hydrogen atmosphere or a mixed gas of an argon gas and a hydrogen gas in a proper fashion, to thereby uniformize a boron concentration in the thickness direction of the surface layer of the silicon wafer doped with boron.

Abstract: The present method provides tools for growing conformal metal nitride, metal carbide and metal thin films, and nanolaminate structures incorporating these films, from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide and transition metal nitride thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures (20) incorporating metal nitrides, such as titanium nitride (30) and tungsten nitride (40), and metal carbides, and methods for forming the same, are also disclosed.

Abstract: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way.

Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

Abstract: There is provided a semiconductor substrate for solid-state image sensing device in which the production cost is lower than that of a gettering method through a carbon ion implantation and problems such as occurrence of particles at a device production step and the like are solved. Silicon substrate contains solid-soluted carbon having a concentration of 1×1016-1×1017 atoms/cm3 and solid-soluted oxygen having a concentration of 1.4×1018-1.6×1018 atoms/cm3.

Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

Abstract: A cleaning process is performed on the surface of a nickel silicide film serving as an underlayer. Then, a Ti film is formed to have a film thickness of not less than 2 nm but less than 10 nm by CVD using a Ti compound gas. Then, the Ti film is nitrided. Then, a TiN film is formed on the Ti film thus nitrided, by CVD using a Ti compound gas and a gas containing N and H.

Abstract: The invention relates to a method for simultaneous doping and oxidizing semiconductor substrates and also to doped and oxidized semiconductors substrates produced in this manner. Furthermore, the invention relates to the use of this method for producing solar cells.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S10) of forming a GaN-based semiconductor layer, a step (S20) of forming an Al film on the GaN-based semiconductor layer, a step (S30, S40) of forming a mask layer composed of a material having a lower etching rate than that of the material constituting the Al film, a step (S50) of partially removing the Al film and the GaN-based semiconductor layer using the mask layer as a mask to form a ridge portion, a step (S60) of retracting the positions of the side walls at the ends of the Al film from the positions of the side walls of the mask layer, a step (S70) of forming a protection film composed of a material having a lower etching rate than that of the material constituting the Al film on the side surfaces of the ridge portion and on the upper surface of the mask layer, and a step (S80) of removing the Al film to remove the mask layer and the protection film formed on the upper surface of t

Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.

Abstract: A SOI substrate includes a silicon substrate, a silicon oxide layer arranged on the silicon substrate, a silicon layer arranged on the silicon oxide layer, a gettering layer arranged in the silicon substrate, and a damaged layer formed of an impurity-doped region arranged in the silicon oxide layer.

Abstract: It has been difficult to manufacture a semiconductor device equipped with a microstructure having a space, an electric circuit for controlling the microstructure, and the like over one substrate. In a semiconductor device, a microstructure and an electric circuit for controlling the microstructure can be provided over one substrate by manufacturing the microstructure in such a way that a structural layer having polycrystalline silicon obtained by laser crystallization or thermal crystallization using a metal element is formed and processed at low temperature. As the electric circuit, a wireless communication circuit for carrying out wireless communication with an antenna is given.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.

Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

Abstract: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 ?m and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.

Abstract: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.

Abstract: The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of the ingots into wafers, annealing of the wafers in a manner that avoids dissociation or decomposition of the wafers. This annealing process is effective to improve transparency of the wafers and/or otherwise remove contaminants from wafers.

Abstract: To expediently and quantitatively estimate Cu within a silicon substrate without fully dissolving the silicon substrate and to ascertain the process contamination, there is provided a method for quantitatively determining the Cu concentration in a Cu containing silicon substrate having obverse and converse surfaces, the silicon substrate contains at least 3×1018 atoms/cm3 of boron and is heated at a temperature of no more than 600° C., the improvement comprises heating the converse surface of the substrate at a temperature between 300° C. to 350° C. for a period of 1 to 12 hours and then quantitatively analyze the Cu concentration at obverse and converse surfaces of the heated substrate.

Abstract: Method of processing a substrate containing at least one semiconductor of the SiXAY type and comprising at least four separate types of light elements, comprising at least the following steps: carrying out a first anneal of the substrate at a temperature T1 corresponding to a thermal activation temperature for a first one of the four types of light elements, carrying out a second anneal of the substrate at a temperature T2 corresponding to a thermal activation temperature for a second one of the four types of light elements, carrying out a third anneal of the substrate at a temperature T3 corresponding to a thermal activation temperature for a third one of the four types of light elements, carrying out a fourth anneal of the substrate at a temperature T4 corresponding to a thermal activation temperature for a fourth one of the four types of light elements, each anneal comprising a holding at the temperature T1, T2, T3 or T4 and the temperatures T1, T2, T3 and T4 being such that T1>T2>T3>T4.

Abstract: A silicon wafer is produced by subjecting a back face of a silicon wafer after the formation of a device structure to a given surface treatment so as to form a gettering sink layer having a good deflective strength.

Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.

Abstract: This p-type silicon wafer was subjected to heat treatment to have a resistivity of 10 ?·cm or more, a BMD density of 5×107 defects/cm3 or more, and an n-type impurity concentration of 1×1014 atoms/cm3 or less at a depth of within 5 ?m from a surface of the wafer. This method for heat-treating p-type silicon wafers, the method includes the steps of: loading p-type silicon wafers onto a wafer boat, inserting into a vertical furnace, and holding in an argon gas ambient atmosphere at a temperature of 1100 to 1300° C. for one hour; moving the wafer boat to a transfer chamber and discharging the silicon wafers; and transferring to the wafer boat silicon wafers to be heat treated next, wherein after the discharge of the heat-treated silicon wafers, the silicon wafers to be heat-treated next are transferred to the wafer boat within a waiting time of less than two hours.

Abstract: A silicon substrate is manufactured from single-crystal silicon which is grown to have a carbon concentration equal to or higher than 1.0×1016 atoms/cm3 and equal to or lower than 1.6×1017 atoms/cm3 and an initial oxygen concentration equal to or higher than 1.4×1018 atoms/cm3 and equal to or lower than 1.6×1018 atoms/cm3 by a CZ method. A device is formed on a front, the thickness of the silicon substrate is equal to or more than 5 ?m and equal to or less than 40 ?m, and extrinsic gettering which produces residual stress equal to or more than 5 Mpa and equal to or less than 200 Mpa is applied to a back face of the substrate.

Abstract: This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.

Abstract: In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.

Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.

Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.

Abstract: By hydrogen-terminating a semiconductor surface using a solution containing HF2? ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.

Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.

Abstract: A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs.

Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

Abstract: A manufacturing method of a semiconductor device with improved operating characteristics and reliability is provided. An amorphous semiconductor film is formed over a substrate, doped with a metal element promoting crystallization, and crystallized by first heat treatment to form a crystalline semiconductor film; a first oxide film formed over the crystalline semiconductor film is removed and a second oxide film is formed; the crystalline semiconductor film having the second oxide film formed thereover is irradiated with first laser light; a semiconductor film containing a rare gas element is formed over the second oxide film; the metal element contained in the crystalline semiconductor film is gettered to the semiconductor film containing a rare gas element by second heat treatment; the semiconductor film containing a rare gas element and the second oxide film are removed; and the crystalline semiconductor film is irradiated with second laser light in an atmosphere containing oxygen.

Abstract: A semiconductor device has an IC chip with a thickness of equal to or less than 100 ?m and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 ?m from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 ?m to 100 ?m. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A method for producing a silicon wafer, comprising performing an activation of metallic impurities by irradiating laser light on the metallic impurities constituting contaminants in the silicon wafer, changing the electric charge of the contaminants, and activating the contaminants to a state such that the contaminants easily react with oxygen precipitation nuclei and are subjected to gettering.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: This invention relates to a process for adjusting the strain in a strained layer on a substrate. The process steps include identifying one or more regions of the strained layer wherein the strain is to be adjusted; implanting elements into at least one of the regions thus identified in the strained layer; annealing the substrate with the strained layer to a temperature maintained for a sufficiently long time to cure crystalline defects caused by the implantation in the implanted region or regions.