Abstract: A method for manufacture of a nanophotonic device can include the step of operatively coupling a planar light source and a photodetector with an optical waveguide. The planar light source, photodetector and optical waveguide can then be monolithically integrated in direct contact with a sapphire substrate, along with an electronic component that is also in direct contact with the sapphire substrate.

Abstract: Measures are introduced to make possible a low-cost packaging of sensor chips having a media access. For this purpose, the sensor chip is first mounted on a substrate and is contacted. The sensor chip is then at least partially embedded in a molding compound. Finally, at least one portion of the media access is produced by the subsequent structuring of the molding compound.

Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: Here, an apparatus is provided. The apparatus generally comprises a substrate and a thermopile. The thermopile includes a cavity that is etched into the substrate, a functional area that is formed over the substrate (where the cavity is generally coextensive with the functional area), and a metal ring formed over the substrate along the periphery of the functional area (where the metal ring is thermally coupled to the substrate).

Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises: applying a sensing layer with variation in a secondary attribute according to heat, on a handle wafer; patterning the sensing layer, thus forming a cavity; forming a sensing part pattern having a beam structure in the cavity; forming a light-absorbing layer for converting energy of incident photons into heat, along the sensing part pattern; turning the entire structure over, removing the handle wafer, and thus exposing a rear portion of the sensing part pattern; and forming an additional light-absorbing layer on a rear portion of the light-absorbing layer formed on the sensing part pattern, thereby forming a sensing structure part having a beam structure.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.

Abstract: An apparatus and method for processing the solar cell substrates is provided. In one embodiment, a laser firing chamber for processing solar cell substrates placed in a carrier, comprising a laser module located at a side of the carrier, the laser module being adapted to generate and direct multiple laser beams over an entire surface of a plurality of solar cell substrates, and a transport adapted to convey the carrier through an outputting region of the laser beams.

Abstract: A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted.

Abstract: A sensor wafer may be configured for in-situ measurements of parameters during an etch process. The sensor wafer may include a substrate, a cover, and one or more components positioned between the substrate and the cover. An etch-resistant coating is formed on one or more surfaces of the cover and/or substrate. The coating is configured to resist etch processes that etch the cover and/or substrate for a longer period than standard thin film materials of the same or greater thickness than the protective coating.

Abstract: A sensor device for sensing air flow speed at the exterior of an aircraft, comprising a substrate having an upper side on which is mounted a diaphragm over an aperture or recess in the substrate, the diaphragm being thermally and electrically insulative, and mounting on its upper surface a heating element comprising a layer of resistive material, and wherein electrical connections to the heating element are buried in the diaphragm and/or the substrate, and provide electrical terminals at the lower side of the substrate. The heating element is exposed to the environment, but the remaining electrical parts of the device are not exposed.

Abstract: A manufacturing method for an infrared sensor includes the following steps: providing a wafer having several chips and a substrate; forming four soldering portions, a thermistor, and an infrared sensing layer on the bottom surface of each chip, wherein the soldering portions are connected electrically to the thermistor and the infrared sensing layer; disposing a soldering material onto at least one bonding location for each soldering portion; backside-etching each chip of the wafer to form a sensing film and a surrounding wall around the sensing film; bonding the wafer and the substrate; heating the soldering materials to connect the substrate and each chip of the wafer; disposing an infrared filter on the surrounding wall of each chip; cutting the wafer and the substrate to form a plurality of individual infrared sensors. The instant disclosure further provides an associated infrared sensor.

Abstract: The invention relates to a method for the manufacture of packaged components. The invention is based here on the problem of facilitating the application of covers with lateral dimensions that are smaller than the lateral dimensions of the functional substrate. For this purpose, a plate-like cover substrate is mounted on a carrier substrate. Then, on the uncovered side of the plate-like cover substrate, trenches are inserted, so that a composite part is obtained with the carrier substrate and individual covering parts that are separated from each other by the trenches, but interconnected by the carrier substrate. The covering parts of the composite part are connected with a functional substrate with a plurality of components. Then, the connection of the covering parts is dissolved with the carrier substrate, and the carrier substrate is removed, so that a composite is obtained with the functional substrate and a plurality of covering parts that cover functional areas.

Abstract: An integrated circuit package system is provided including attaching an external interconnect on a tape; attaching a backside element on the tape adjacent to the external interconnect; attaching an integrated circuit die with the backside element, the backside element is on a first passive side of the integrated circuit die; connecting a first active side of the integrated circuit die and the external interconnect; and forming a first encapsulation over the integrated circuit die with the backside element exposed.

Abstract: A semiconductor device includes a semiconductor element provided over a wiring board; sealing resin configured to seal the semiconductor element; and reinforcing resin provided at least at a part of a boundary part of the sealing resin and the wiring board. In the above-mentioned semiconductor device, the reinforcing resin may be provided along a perimeter of the boundary part of the sealing resin and the wiring board. The reinforcing resin may be provided at a boundary part of the sealing resin and the wiring board in a vicinity of a corner part of the sealing resin.

Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planariza

Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac

Abstract: A method of forming a micro-electro mechanical system (MEMS), includes (1) removing material from a first wafer to define a first movable portion corresponding to an x-y accelerometer and a second movable portion corresponding to a z accelerometer, where each movable portion comprises at least one flexure member and at least one proof mass, each proof mass and flexure member being formed by the selective removal of material from a top side and a bottom side of first wafer; (2) bonding the first wafer to a second wafer comprising an electronic circuit, such that a gap is defined between the first wafer and the second wafer. The thickness of the at least one flexure member of the first movable portion is independent of a thickness of the at least one flexure member of the second movable portion and a thickness of the proof mass of the first movable portion is independent of a thickness of the at least one proof mass of the second movable portion.

Abstract: Certain example embodiments provide techniques for improving the output of hybrid systems comprising photovoltaic (PV) and thermoelectric (TE) modules in conjunction with super-insulating, yet optically transmissive, vacuum insulated glass (VIG) unit technologies. More particularly, certain example embodiments relate to hybrid systems including hydrogenated microcrystalline silicon (mc-Si), hydrogenated amorphous silicon (a-Si), bulk hetero junction solar cell, and/or the like, that may be used together with a TE generator, that achieves high operational PV and TE efficiencies under ambient conditions. In that regard, certain example embodiments effectively partition the solar spectrum in order to yield an increased conversion efficiency of a PV-TE hybrid system with a solar cell operating at ambient temperature.

Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 ? to about 1,000 ?, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.

Abstract: A thermal absorption structure of a radiation thermal detector element may include an optically transitioning material configured such that optical conductivity of the thermal absorption structure is temperature sensitive and such that the detector element absorbs radiation less efficiently as its temperature increases, thus reducing its ultimate maximum temperature.

Abstract: A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer.

Abstract: The present invention discloses a method of encapsulating a wafer level microdevice, which includes: fabricating a microdevice on top side of a first silicon wafer; depositing a first capping carbon film on the top side of the first silicon wafer; implementing a backside fabricating process of wafer from bottom side of the first silicon wafer by carrying the top side of the first silicon wafer through the first capping carbon film; removing the first capping carbon film by selective gaseous reaction with carbon; and encapsulating an encapsulation wafer onto the top side of the first silicon wafer. The present invention deposits and removes the first capping carbon film by means of chemical technology, thereby protecting the microdevice on the top side of the first wafer during implementing the backside fabricating process of wafer.

Abstract: A method for manufacturing a thermoelectric module that involves obtaining a first printed circuit board having a first dielectric layer sandwiched between a first metallic substrate and a first electrical conductive layer, obtaining a second printed circuit board that comprises a second dielectric layer sandwiched between a second metallic substrate and a second electrical conductive layer, and positioning a plurality of N-type and P-type thermoelectric elements having first ends and second ends between the first and second electrical conduction layers so that the first ends of the thermoelectric elements are situated on the first electrical conductive layer and the second ends of the thermoelectric elements are situated on the second electrical conductive layer and arranged to form an electrical circuit that alternates between the N-type and P-type thermoelectric elements.

Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

Abstract: A method of bonding an integrated circuit to an adhesive substrate. The integrated circuit is one of a plurality of integrated circuits, each having a respective frontside releasably attached to a film frame tape supported by a wafer film frame. The method includes the steps of: (a) selecting one of the integrated circuits for bonding to the adhesive substrate; (b) positioning the adhesive substrate at a backside of the selected integrated circuit; (c) positioning a bonding tool on a zone of the film frame tape, the zone being aligned with the selected integrated circuit; and (d) applying a bonding force from the bonding tool through the film frame tape and the selected integrated circuit onto the adhesive substrate, so as to bond the backside of the selected integrated circuit to the substrate.

Abstract: A wafer-type temperature sensor may include a wafer for temperature detection; a circuit board bonded to one surface of the wafer for temperature detection; at least one temperature data detector provided on the one surface of the wafer for temperature detection and capable of detecting temperature data; and a temperature detecting unit mounted on the circuit board and capable of detecting a temperature of the wafer for temperature detection from the temperature data detected by the temperature data detector. Here, a difference between a linear expansion coefficient of the circuit board and a linear expansion coefficient of the wafer for temperature detection may be equal to or less than a predetermined value.

Abstract: A semiconductor package includes a semiconductor die. Encapsulant is flowed around a portion of the semiconductor die. The encapsulant is etched and a conductive material is deposited into the etched portion of the encapsulant to form a thermally conductive structure. In one embodiment, a trench is etched into the encapsulant and a thermally conductive material is deposited into the trench to form a thermal channel. In alternative embodiments, thermally conductive through hole vias (THVs) are formed in the encapsulant. A thermally conductive pad may be formed over the semiconductor die to facilitate removal of heat energy from the hot spots of the semiconductor die. A thermally conductive trace is formed to interconnect the thermal channel and the thermally conductive pad. A heat sink may be deposited over the semiconductor package. The packages are singulated by cutting through the encapsulant or the thermal channel.

Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.

Abstract: A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.

Abstract: Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.

Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.

Abstract: A method of manufacturing a micro-electrical-mechanical system with thermally isolated active elements. Such a system may embody a bolometer, which is well suited for detecting electromagnetic radiation between 90 GHz and 30 THz while operating at room temperature. The method also discloses a generalized process for manufacturing circuitry incorporating active and passive micro-electrical-mechanical systems in a silicon wafer.

Abstract: An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: An optical device includes a semiconductor substrate (11) on which a light receiving part (12) (or a light emitting part) and electrodes (13) are formed, and a translucent plate (2) bonded on the light receiving part (12) with a translucent adhesive (5), the semiconductor substrate (11) having a plurality of convex portions (31) formed so as to separate the light receiving part (12) and the electrodes (13) and have proper gaps (32) therebetween.

Abstract: A thermoelectric conversion module includes: p-type semiconductor blocks, each including a p-type thermoelectric conversion material, a first column portion and a first coupling portion that projects in a horizontal direction from an end of the first column portion; and n-type semiconductor blocks, each including an n-type thermoelectric conversion material, a second column portion and a second coupling portion that projects in a horizontal direction from an end of the second column portion, wherein the first coupling portions of the p-type semiconductor blocks are respectively coupled to the other ends of the second column portions of the n-type semiconductor blocks, and the second coupling portions of the n-type semiconductor blocks are respectively coupled to the other ends of the first column portions of the p-type semiconductor blocks, and the p-type semiconductor blocks and the n-type semiconductor blocks are alternately arranged and coupled to each other in series.

Abstract: A thermoelectric generator may comprise a pair of thermally conducive top and bottom plates having a foil assembly positioned therebetween. The foil assembly may comprise a substrate having a series of alternating thermoelectric legs formed thereon. The thermoelectric legs may be formed of alternating dissimilar materials arranged in at least one row. Each one of the thermoelectric legs may define a leg axis oriented in non-parallel relation to the row axis. Thermally conductive strips mounted on opposite sides of the substrate may be aligned with opposite ends of the thermoelectric legs in the rows such that one end of the thermoelectric legs is in thermal contact with the top plate and the opposite end of the thermoelectric legs is in thermal contact with the bottom plate. The thermally conductive strips define thermal gaps between the thermoelectric legs and the top and bottom plates causing heat to flow lengthwise through the thermoelectric legs resulting in the generation of electrical voltage.

Abstract: By providing thermoelectric elements, such as Peltier elements, in a semiconductor device, the overall heat management may be increased. In some illustrative embodiments, the corresponding active cooling/heating systems may be used in a stacked chip configuration to establish an efficient thermally conductive path between temperature critical circuit portions and a heat sink of the stacked chip configuration.

Abstract: In one embodiment, an operating condition of a thermoelectric module is monitored. It is determined when the monitored operating condition exceeds a desired range. Upon determining the monitored operating condition exceeds the desired range, a thermal adjustment is applied to the thermal condition to direct the operating condition to within the desired range. The monitoring the operating condition may include measuring an operating temperature of an environment adjacent a surface of the thermoelectric module, a surface temperature of a portion of the thermoelectric module, a thermal differential between the first surface and the second surface of the thermoelectric module, and an output voltage of the thermoelectric module. The desired range includes a temperature range below a level at which the thermoelectric module will sustain thermal damage and a thermal differential capable of causing the thermoelectric module to generate a minimum desired output voltage.

Abstract: A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.

Abstract: A method for packaging a sensor device having a sensitive structure integrated on a semiconductor chip is provided. When molding the device package, an inward extending section of the mold maintains an access opening to the sensor. A buffer layer is arranged on the chip between the inward extending section and the sensitive structure. The buffer layer protects the sensitive structure from damage by the inward extending section and acts as a seal while casting the housing. The buffer layer also covers at least part of the semiconductor electronic components of the circuitry integrated onto the chip. By covering these components, mechanical stress, as it is e.g. caused by different thermal expansion coefficients of the packaging and the chip, can be reduced.

Abstract: A light engine kernel for a light emitting diode (LED) includes a solid body of transparent material having an index of refraction of at least 1.5. The body has a domed, light-emitting top that is an inverted parabola of revolution, a reflective sidewall that is a compound parabolic concentrator (CPC), and a cavity at a focus of the CPC that is adapted to receive an LED. The domed top may include a phosphor coating of a yellow-emitting phosphor. The cavity may be adapted to receive only a single LED or plural LEDs of the same or different colors on a board. The kernel and LED are not integrally formed, reducing thermal degradation of the phosphor coating and improving application flexibility.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

Abstract: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young's modulus than the material of the first and second chips.

Abstract: A method of forming a device with multiple encapsulated pressures is disclosed herein. In accordance with one embodiment of the present invention, there is provided a method of forming a device with multiple encapsulated pressures, including providing a substrate, forming a functional layer on top of a surface of the substrate, the functional layer including a first device portion at a first location, and a second device portion at a second location adjacent to the first location, encapsulating the functional layer, forming at least one diffusion resistant layer above the encapsulated functional layer at a location above the first location and not above the second location, modifying an environment adjacent the at least one diffusion resistant layer, and diffusing a gas into the second location as a result of the modified environment.

Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.

Abstract: A method for creating an array of thermoelectric elements includes applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers. A P/N-type ingot is formed from the coated P-type wafers and the coated N-type wafers. The coated P-type wafers and the coated N-type wafers are alternatingly arranged in the P/N-type ingot. P/N-type wafers comprising P-type elements and N-type elements are sliced from the P/N-type ingot and a second coating of the dielectric material is applied to the P/N-type wafers to form coated P/N-type wafers. Furthermore, a P/N-type array from the coated P/N-type wafers.

Abstract: A method for fabricating a sealed cavity microstructure comprises the steps of: forming an insulation layer with a micro-electro-mechanical structure on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one suspended structure and at least one conductive structure between which is disposed a spacer region; after an etching, filling a sacrificial layer into the spacer region and on the surface of the conductive structure; forming holes in the sacrificial layer correspondingly to the conductive structure; depositing a cap layer into the holes and the surface; after removing the sacrificial layer, utilizing the clearance of the cap layer to carry out a further etching to realize the suspension of the micro-electro-mechanical structure; and finally, utilizing a sealing layer to achieve the sealing effect. By such arrangements, the exposure of the micro-electro-mechanical structure can be effectively prevented, and the final package cost can be reduced.