Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

Abstract: A thermionic or thermotunneling generator or heat pump is disclosed, comprising electrodes substantially facing one another and separated by spacers disposed between the electrodes, wherein the substrate material for the cathode is preferably a single crystalline silicon wafer while the substrate for the anode is an organic wafer, and preferably a polished polyimide (PI) wafer. On the cathode side, standard silicon wafer processes create the 10-1000 nm thin spacers and edge seals from thermally grown oxide. Either wafer is partially covered with a thin film of material that is characterized by high electrical conductivity and low work function. In one embodiment, the cathode is partially covered with a thin film of Ag—Cs—O. In another embodiment, the anode is additionally covered with a thin film of Ag—Cs—O, in which case the work function of the cathode coating material is reduced further utilizing an Avto Metal structure of nanoscale patterned indents.

Abstract: A method for manufacturing a hermetically sealed micro-device package encapsulating a micro-device. The package includes a transparent window allowing light to pass into and out of a cavity containing the micro-device. A first frame-attachment area is prepared on semiconductor substrate having a micro-device operably disposed thereupon, the first frame-attachment area having a plan that circumscribes the micro-device. A second frame-attachment area is prepared on a sheet of transparent material, the second frame-attachment area having a plan that circumscribes a window aperture portion of the sheet.

Abstract: A method for creating an array of thermoelectric elements includes applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers. A P/N-type ingot is formed from the coated P-type wafers and the coated N-type wafers. The coated P-type wafers and the coated N-type wafers are alternatingly arranged in the P/N-type ingot. P/N-type wafers comprising P-type elements and N-type elements are sliced from the P/N-type ingot and a second coating of the dielectric material is applied to the P/N-type wafers to form coated P/N-type wafers. Furthermore, a P/N-type array from the coated P/N-type wafers.

Abstract: A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.

Abstract: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.

Abstract: A circuit with embedding components (13) is produced by placing the components (13) on a substrate (14) and applying sheets (15) of prepreg. The prepreg sheets (15) have apertures to accommodate the -components, the number of sheets and arrangement of apertures being chosen to accommodate a variety of component X, Y and Z dimensions. A top layer with Cu foil (16(b)) is applied. The assembly is pressed in an operation analogous to conventional multilayer board lamination pressing. This causes all of the prepreg resin to flow to completely embed the components without raids or damage. Electrical connections are made by drilling and plating vias.

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer.

Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (122), which is glass in the case of many DMD packages, seals the device (100) in package cavity (120).

Abstract: The present invention provides an one-pack thermosetting type epoxy resin composition which is useful as an underfilling material used when a flip chip or a semiconductor package comprised of a semiconductor element held on a carrier base being mounted onto a wiring substrate; which can omit a fluxing process as adopted for improvement of the bonding force of bumps or solder balls particularly at said mounting and exhibits a good voidless property even at a reflow temperature; and which can be also applied as an adhesive, a paint, a coating material, a sealing material, or the like. The one-pack thermosetting type epoxy resin composition of the present invention comprises as essential ingredients, a liquid epoxy resin and a carboxylic acid having two or more carboxylic groups in molecule as a curing agent.

Abstract: Disclosed herein are a semiconductor package used in digital optical instruments and a method of manufacturing the same. The semiconductor package comprises a wafer made of a silicon material and having pad electrodes formed at one side surface thereof, an IR filter attached on the pad electrodes of the wafer by means of a bonding agent, terminals electrically connected to the pad electrodes, respectively, in via holes formed at the other side surface of the wafer, which is opposite to the pad electrodes, and bump electrodes, each of which is connected to one side of each of the terminals. The present invention is capable of minimizing the size of a semiconductor package having an image sensor, which is referred to as a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD), through the application of a wafer level package technology, thereby reducing the manufacturing costs of the semiconductor package and accomplishing production on a large scale.

Abstract: A hybrid electronic circuit package (102, FIG. 1) includes non-insertable conductive features (110) and insertable conductive features (112) at a surface of the package. A hybrid receptacle (120), such as a socket, for example, includes non-insertable contacts (124) and insertable contacts (126), which are positioned in a complementary manner with the non-insertable and insertable features of the package. A vertical securement device (132, 134, 136) applies a vertical compressive force to the package (102) to compress the non-insertable features (110) against the non-insertable contacts (124). Further, a normal force securement device can be used to provide a sustained normal force to compress the insertable features and contacts together. In one embodiment, the non-insertable features are land grid array lands and the insertable features are low insertion force features.

Abstract: The present invention provides an electric power generation method using a thermoelectric power generation element, a thermoelectric power generation element, and a thermoelectric power generation device, each of which has high thermoelectric power generation performance and can be used for more applications. The thermoelectric power generation element includes a first electrode and a second electrode that are disposed to oppose each other, and a laminate that is interposed between the first and second electrodes and that is electrically connected to both the first and second electrodes, where the laminate has a structure in which SrB6 layers and metal layers containing Cu, Ag, Au, or Al are laminated alternately, a thickness ratio between the metal layer and the SrB6 layer is in a range of metal layer: SrB6 layer=20:1 to 2.

Abstract: A method is provided for aligning parts such as MEMS devices and photonics devices. One approach involves: providing between first and second parts a bonding material having fluid and solid states; applying a control field in the region of the bonding material, the bonding material changing its shape in direct response to changes in the control field while in the fluid state; adjusting the control field while the bonding material is in the fluid state so that the bonding material changes shape and causes relative movement of the first and second parts; and thereafter causing the bonding material to transition from the fluid state to the solid state while the first and second parts are in a selected position with respect to each other.

Abstract: According to the invention, a layer made of an electrically insulating material is applied to a substrate and a component that is arranged thereupon in such way that said layer follows the surface contour formed by the substrate and the component.

Abstract: To provide a circuit device freed from constrains of a mounting direction. The circuit device according to the present invention includes: a conductive pattern for forming a die pad, a first bonding pad, and a second bonding pad; and a semiconductor element (TR) attached to the conductive pattern. The circuit device further includes: a sealing resin for covering the semiconductor element (TR) and the conductive pattern with a rear surface of the conductive pattern being exposed; and a coating resin for covering the rear surface of the conductive pattern exposed from the sealing resin. The rear surface of the conductive pattern is exposed from openings of the coating resin, and the openings are arranged with rotational symmetry about a central point of the circuit device.

Abstract: Phosphonate surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirror devices. The surfactants are adsorbed from vapor or solution to form self-assembled monolayers at the device surface. The higher binding energy of the phosphonate end groups (as compared to carboxylate surfactants) improves the thermal stability of the resulting layer.

Abstract: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape and exposing bonding pads of the chip on the active surface respectively. Conductive material is deposited into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively. A multi-layered interconnection structure is formed on the tape on the opposite of the chip, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

Abstract: An embodiment of the present invention related to fingerprint sensors is described. The sensor comprises an integrated-circuit chip having a sensitive surface, a substrate provided with electrical connections and wire-bonding wires connecting the chip to the electrical connections. The sensor further includes a molded protective resin at least partly covering the substrate and the chip and completely encapsulating the wire-bonding wires. The resin forms, on at least one side of the chip and at most three sides, a bump rising to at least 500 microns above the sensitive surface, this bump encapsulating the wire-bonding wires and constituting a guide for a finger, the fingerprint of which it is desired to detect.

Abstract: In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and has conductive traces formed thereon. A soldermask is received on the one side, and has a plurality of openings formed therethrough to locations on the conductive traces. The soldermask includes a peripheral elongated trench therein positioned on the one side to align with at least a portion of an elongated mold void perimeter of a transfer mold to be used for transfer mold packaging of the one side. In one implementation, the invention includes a transfer mold semiconductor packaging process. In one implementation, the invention includes a semiconductor package. In one implementation, the invention includes a ball grid array.

Abstract: A microdevice (20) having a hermetically sealed cavity (22) to house a microstructure (26). The microdevice (20) comprises a substrate (30), a cap (40), an isolation layer (70), at least one conductive island (60), and an isolation trench (50). The substrate (30) has a top side (32) with a plurality of conductive traces (36) formed thereon. The conductive traces (36) provide electrical connection to the microstructure (26). The cap (40) has a base portion (42) and a sidewall (44). The sidewall (44) extends outwardly from the base portion (42) to define a recess (46) in the cap (40). The isolation layer (70) is attached between the sidewall (44) of the cap (40) and the plurality of conductive traces (36). The conductive island (60) is attached to at least one of the plurality of conductive traces (36). The isolation trench (50) is positioned between the cap (40) and the conductive island (60) and may be unfilled or at least partially filled with an electrically isolating material.

Abstract: The yield of a sealing process for a semiconductor device which adopts a flip-chip mounting method is to be improved. In a molding process wherein plural semiconductor chip ICs mounted on a parts mounting surface of a substrate matrix through bump electrodes are to be sealed all together with a sealing resin in a reduced state of the internal pressure of a cavity of a molding apparatus, a clamping pressure at the time of clamping the substrate matrix by both a lower die and an upper die of a molding die is set at a relatively low pressure in an initial stage of injection of the sealing resin and is changed to a relatively high pressure when the sealing resin has covered the semiconductor chip ICs located in a final stage in the resin injecting direction.

Abstract: A process for producing a thin film with MEMS probe circuits by using semiconductor process technology comprises steps of providing a flatted process substrate; forming a separable interface on the flatted process substrate; forming a probe circuit thin film with electric circuits, probes and circuit contacts on the separable interface; forming a raised probe supported-spacer on the probe circuit thin film; separating the probe circuit thin film from the process substrate; and processing a subsequent microstructure working to obtain a thin film with MEMS probe circuits which use the raised probe supported-spacer to form a buffer to prevent the probes from being exposed to much pressure.

Abstract: The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on a substrate; a covering having a top part and an extension extending a distance from the top part from the top part, an adhesive that is used to bond the extension portion of the covering to the substrate; and a sealing agent for hermetically sealing the area where the covering extension is bonded to the substrate. In the method of the invention the sealing agent is applied using atomic layer deposition techniques.

Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.

Abstract: A surface mounted package for semiconductor die has a lead frame with a first and elongated die pad which receives three MOSgated die spaced along its length; second, third and fourth die pads laterally spaced from the first die pad and in a row parallel to the first die pad and receiving respective MOSgated die. A central wire bond receiving pad is disposed between the first pad and the spaced second, third and fourth pads. Wire bonds then connect the die into a three phase inverter circuit. Pin connectors extend through a plastic housing covering the top of the lead frame and are connectable, with the die pads, to the surface of a PCB.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: A method for manufacturing a pressure sensor includes the steps of: preparing a semiconductor substrate; forming an insulation film on the substrate; forming a first metal film on the insulation film; forming a first protection film on the first metal film and the insulation film; forming a second protection film on the first metal film and the first protection film; performing reduction treatment of adhesive force on the second protection film, the force between the second protection film and a second metal film; forming the second metal film on the first metal film and the first protection film; and removing a part of the second metal film.

Abstract: An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff therebetween. Wire bonds may then be formed between bond pads on the semiconductor die to conductive pads or terminals on the carrier substrate. With this arrangement, a dielectric filler material is disposed in the gap or standoff to form a permanent bonding agent between the semiconductor die and the carrier substrate. By applying the dielectric filler material after forming the wire bonds, the dielectric filler material coats at least a portion of the wire bonds to stabilize the wire bonds and prevent wire sweep in an encapsulation process, such as transfer molding, performed thereafter.

Abstract: A method of fabricating an X-ray detector array element. A gate and a gate insulation layer are formed on a substrate. A silicon island is formed on the insulation layer in a transistor area. A common line is formed on the insulation layer, simultaneously; source and drain are formed on the island to form a TFT. A bottom electrode is formed on the insulation layer in a capacitor area and covers the common line. A passivation layer is formed on the insulation layer, the bottom electrode and the TFT. A first via hole penetrates the passivation layer to expose the source. A planarization layer is formed on the passivation layer and fills the first via hole. Second and third via holes penetrate the planarization layer. The second via hole exposes the source. The third via hole exposes part of the passivation layer. A top electrode is formed on the planarization layer and connects the source.

Abstract: A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

Abstract: A protective device for subassemblies having a substrate and at least one component to be protected which is disposed on the substrate includes at least one covering element for covering a subassembly. An expanded filler material fills at least one given space between the substrate and the covering element and provides protection against mechanical compression. A method of producing a protective device is also provided. An expandable material is applied to the substrate and is expanded after the covering element has been mounted.

Abstract: A semiconductor card is made by a disclosed method which, in one molding step, forms a plastic body on a substrate attached to a surrounding frame by narrow connecting segments spanning a peripheral opening. The connecting segments are motivated downward by pins outside of the card periphery, holding the substrate against a lower level of the mold cavity during molding. Molded wings extending laterally from the card periphery are also formed. Following molding and curing, the casting is removed and the card singulated by excising the wings from the card. The resulting card has smooth edge surfaces and precise dimensions. Separate glob top encapsulation is avoided.

Abstract: Method for encapsulating a chip with encapsulant, one portion of the surface of which chip must remain free of encapsulant, comprising the following steps: fixing the chip on a carrier with a suitable conductor structure, placing carrier and chip in one part of a mould, positioning a material on the mould or the chip surface, such that this material is clamped between the chip and mould after the mould has been closed, closing the mould, introducing the encapsulant and at least partially curing the encapsulant. The material is a heat-resistant moulding, having dimensions in the directions parallel to the surface of the chip such that an accurately delimited portion of the chip surface will be covered when the mould is closed, and a dimension in the direction perpendicular to the chip surface determined by the distance between the mould surface and the free portion of the chip surface.

Abstract: The present invention provides a printed circuit board which is capable of air-tightly sealing a functional surface of a device and of preventing excessive stress from acting on the device itself or a conductive bump conjugating the device with a wiring board and a method of fabricating the printed circuit board. The printed circuit board has a device mounted in a hollow formed in a wiring board via a plurality of conductive bumps. In the printed circuit board, a gap is formed between a functional surface of the device and an inner surface of the hollow, and a sealing member is disposed around side surfaces of the device so as to air-tightly isolate the gap and a space within the hollow excepting the gap.

Abstract: A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: A micromechanical component having a substrate beneath at least one structured layer, in the structured layer at least one functional structure being formed, a cap which covers the functional structure, between the cap and the functional structure at least one cavity being formed, and a connecting layer which connects the cap to structured layer, as well as a method for producing the micromechanical component. To obtain a compact and robust component, the connecting layer is formed from an anodically bondable glass, i.e. a bond glass, which has a thickness in the range of 300 nm to 100 ?m, which may in particular be in the range of 300 nm to 50 ?m.

Abstract: This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer. The process involves extending the layers of sacrificial material past the horizontal boundaries of the cap layer. The cap layer is supported by pillars formed by a deposition in holes etched through the sacrificial layers, and the etchant entry holes are formed when the excess sacrificial material is etched away, leaving voids between the pillars supporting the cap.

Abstract: In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and has conductive traces formed thereon. A soldermask is received on the one side, and has a plurality of openings formed therethrough to locations on the conductive traces. The soldermask includes a peripheral elongated trench therein positioned on the one side to align with at least a portion of an elongated mold void perimeter of a transfer mold to be used for transfer mold packaging of the one side. In one implementation, the invention includes a transfer mold semiconductor packaging process. In one implementation, the invention includes a semiconductor package. In one implementation, the invention includes a ball grid array.

Abstract: The invention provides a two part mold for forming wafer scale caps. The mold has a first half and a second half. The first half and second half, when brought together defining mold cavities for wafer scale caps. The caps have central areas surrounded by sidewalls and the side walls having free edges. In preferred embodiments, the mold is made from a semiconductor material.

Abstract: A method for forming a patterned silicon bearing material, e.g., silicon substrate. The method includes providing a silicon substrate, which has a surface region and a backside region. The method includes forming a plurality of recessed regions on the surface region. Each of the plurality of recessed regions has a border region. Preferably, the plurality of recessed regions forms a patterned surface region. The method includes bonding (e.g., hermetic bonding or on-hermetic seal) the patterned surface region to a handle surface region of a handle substrate, e.g., glass substrate. Each of the border regions, which protrude outwardly from the recessed regions, is bonded to the handle surface region, while each of the recessed regions remain free from attachment to any surface of the handle surface region. The method includes etching selected regions on the backside to remove a thickness of silicon substrate overlying each of the recessed regions.

Abstract: A sealing apparatus for a semiconductor wafer includes an upper mold and a lower mold. The lower mold includes a recess in which the semiconductor wader is placed, and a pot for introducing resin to the recess. The pot is located under a center area of the recess. Thus, when the resin is introduced in the recess, the resin is spread from the center area of the semiconductor wafer toward the peripheral area.

Abstract: A mass-production packaging means suitable for mass-production packaging of an organic luminescent display. An organic electroluminescent display panel on which an organic luminescent device has been formed is first provided. Then, an UV laser is used to clean the surface of the organic electroluminescent display panel. A molding compound is applied on the organic electroluminescent display panel by a sizing system. Subsequently, a lid is aligned with the organic electroluminescent display panel and lamination is performed. Finally, the molding compound is irradiated with UV light to be cured. The package is thus completed.

Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

Abstract: A microfabricated vacuum sensor may be formed using semiconductor integrated circuit processes. The sensor may be formed inside an enclosure with a microfabricated component. The sensor may then be used to measure the pressure within the enclosure.

Abstract: A microelectromechanical device and a method for producing it having at least one layer on a substrate, in particular a thermoelectric layer on a substrate, the thermal expansion coefficient of the at least one layer and the thermal expansion coefficient of the substrate differing greatly. The at least one layer is coupled to at least one stress reduction means for the targeted reduction of lateral mechanical stresses present in the layer. This achieves a stress-free layer or enables stress-free growth.

Abstract: A fingerprint sensor may include a plurality of electrostatic discharge (ESD) electrodes carried by a dielectric layer of a fingerprint sensing portion. The fingerprint sensing portion is for sensing a fingerprint of a user. The fingerprint sensing portion may include the dielectric layer, and, in some embodiments, may also include an array of sensing electrodes also carried by the dielectric layer. Accordingly, each ESD electrode may be interposed between adjacent sensing electrodes. The ESD electrodes attract ESD events and dissipate the energy therein to avoid damaging adjacent sensing electrodes and/or portions of the dielectric layer. The fingerprint sensor may also include an electrically conductive layer connected to the ESD electrodes, which may provide a convenient ground plane, for example, for removing ESD energy from the fingerprint sensor. The electrically conductive layer may extend beneath the sensing electrodes.

Abstract: A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.