Abstract: Embodiments of a micro electro mechanical system are disclosed.

Abstract: A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.

Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: In a device for the detection of thermal radiation which and a method for production of such a device, a stack is formed with at least one detector support having at least one detector element for the conversion of the thermal radiation into an electric signal, at least one circuit support with at least one read-out circuit for reading out the electrical signal and at least one cover to shield the detector element, wherein the detector support and the cover are so arranged with respect to one another that a first stack cavity bounded by the detector support and the cover is provided between the detector element of the detector support and the cover and that the circuit support and the detector support are so arranged with respect to one another that at least one second stack cavity bounded by the circuit support and the detector support is provided between detector support and the circuit support and that the first hollow stack support and/or the second stack cavity is evacuated or can be evacuated.

Abstract: An end point detection method in the case where a catalyst arranged in a treatment chamber of a gas phase reaction processing apparatus is heated at high temperature by supplying electric power thereto and the treatment is carried out by cracking a reaction gas by the catalyst heated at high temperature, comprises the steps of supplying the electric power to the catalyst from a constant current source, detecting electric potential difference between both ends of the catalyst, performing primary differentiation of the detected electric potential difference, and determining an end point of the treatment based on obtained primary differential value.

Abstract: A semiconductor device includes a pair of power chips, an IC chip, a plurality of leads one of which having a die pad on which the power chips are mounted and another one having a die attach portion on which the IC chip is mounted, a resin sheet firmly adhered to one side of the die pad, and a resin casing made by molding operation to encapsulate the power chips, the IC chip and the resin sheet by a resin in such a manner that one surface of the resin sheet opposite the die pad is exposed to the exterior of the resin casing. The resin casing has a groove formed in one surface opposite the exposed surface of the resin sheet, the groove extending parallel to the resin sheet and perpendicular to a runner through which the resin was supplied in the molding operation.

Abstract: A mold structure for packaging LED chips includes a top mold and a bottom mold. The bottom mold is mated with the top mold. The bottom mold has a main flow channel, a plurality of receiving spaces formed beside the main flow channel, a plurality of secondary flow channels for respectively and transversely communicating the receiving spaces with each other, and a plurality of ejection pins penetrating through the bottom mold.

Abstract: A universal micro-electro mechanical (MEM) device package is provided as having a relatively thin silicon-on-insulator (SOI) wafer having a top surface and a bottom surface. At least on MEM device maybe disposed on the top surface of the SOI wafer. A support member may be disposed on predetermined portions of the top surface of the SOI wafer to substantially surround the MEM device. A cap layer may be positioned over and in contact relationship with the support member. In this arrangement, the support member cooperates with the cap layer and predetermined portions of the top surface of the SOI wafer to form a hermetically sealed chamber surrounding the MEM device.

Abstract: A method for manufacturing a laser device includes fixing a laser chip to a holder via a metal having a low melting point by melting the metal at a temperature higher than the melting point, heating the holder to which the laser chip is fixed at a heat treatment temperature that is lower than the melting point and, thereafter, sealing the laser chip by covering the holder to which the laser chip is fixed with a cap. The heating step may be performed in an atmosphere in which ozone is generated or an atmosphere in which oxygen plasma is generated. Furthermore, the holder to which the laser chip is fixed is covered with a cap to make a hermetically sealed package in dry air or an inert gas, and then an ultraviolet ray is irradiated into the package while it is heated.

Abstract: In a method of manufacturing a semiconductor device of the invention, a rigid substrate which supports one or more semiconductor elements on a surface of the substrate and is clamped between an upper mold and a lower mold of an encapsulation mold at a time of resin encapsulation is provided, so that a vent-end edge portion of the substrate corresponding to a vent end of the encapsulation mold has a thickness smaller than a thickness of other portions of the substrate. The substrate is disposed in the encapsulation mold, and resin is injected into a cavity between the upper mold and the substrate to encapsulate the semiconductor elements with the resin.

Abstract: A thermoelectric device including a first substrate, a plurality of conductive vias, a second substrate, a thermoelectric couple module, a first insulation layer, and a second insulation layer is provided. The first substrate has a first surface and a second surface opposite to each other. The conductive vias running through the first substrate respectively connect the first and the second surface. The second substrate faces the second surface of the first substrate. The thermoelectric couple module including a plurality of thermoelectric couples connected with each other in series is disposed between the first and the second substrate and coupled to the conductive vias. The first insulation layer is disposed between the thermoelectric couple module and the first substrate. The second insulation layer is disposed between the thermoelectric couple module and the second substrate.

Abstract: A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.

Abstract: One aspect is a composite board including semiconductor chips in semiconductor device positions and a plastic housing composition partly embedding the semiconductor chips. A mould is provided for surrounding the semiconductor chips with plastic housing composition, the mould having a lower part and an upper part and a moldings cavity and the molding cavity having an upper contact area, which forms an interface with the top side of the plastic housing composition to be applied. The upper contact area is covered with a parting layer having essentially the same surface constitution and the same thermal conductivity as an adhesive film forming an interface with the underside of the plastic housing composition, with the result that a warpage of the composite board of less than 1% is obtained.

Abstract: Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity.

Abstract: A temperature sensor with a bandgap circuit is provided. The bandgap circuit is covered by a buffer layer of photoresist. The device is packaged in a housing. By providing the buffer layer, mechanical stress in the bandgap circuit, as it is e.g. caused by different thermal expansion coefficients of the packaging and the chip, can be reduced. This improves the accuracy of the device.

Abstract: Disclosed herein is a method for manufacturing a feed thru for use in an electrolytic capacitor case. First, an electrode is inserted into a liquid injection mold. Liquid elastomer is then injected into the mold to surround a portion of the electrode. The elastomer is cured, and the resulting electrode and feed thru combination is inserted into a machined hole in a capacitor case. The machined hole may be located on either the base or the lid of the capacitor case. In other embodiments, a ferrule may also be placed in the liquid injection mold prior to injecting liquid elastomer. When a ferrule is used, the assembly may be welded into a machined hole in a capacitor case.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming a first interlayer dielectric (ILD) layer on the p-type and n-type semiconductors, exposing top surfaces of the n-type and p-type semiconductors, forming a third silicide layer on one semiconductor on each of the first and second silicide layers, forming a second ILD layer on the third silicide layer, and etching the second and first ILD layers to form contact holes exposing top surfaces of the first and second silicide layers.

Abstract: A method of bonding an integrated circuit to a substrate is provided. The integrated circuit is one of a plurality of integrated circuits, each having a respective frontside releasably attached to a film frame tape supported by a wafer film frame. The method comprises the steps of: (a) positioning a substrate at a backside of the integrated circuit; (c) positioning a bonding tool on a zone of the film frame tape, the zone being aligned with the integrated circuit; and (c) applying a bonding force from the bonding tool, through the film frame tape and the integrated circuit, onto the substrate.

Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.

Abstract: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted to the metal portion; (4) polishing a surface of the substrate to make a height of the polymer composite portion equal to that of the metal portion; (5) forming a covering material on the surface of the substrate; and (6) cutting the substrate via the polymer composite portion for decreasing cutting bur produced on the metal portion. Furthermore, the method is provided for combining the metal substrate and the polymer composite material, thereby to increase cutting precision and strength of the substrate structure.

Abstract: A method of manufacturing a hermetically-sealed chamber with an electrical feedthrough includes the step of hermetically fixing an electrode to a substrate in a predetermined location on the substrate. A passage is formed through the substrate through the predetermined location such that at least a portion of the electrode is exposed to the passage. The passage is then at least partially filled with an electrically conductive material. A housing is then formed including the substrate such that the housing defines a chamber, with the electrode being disposed within the housing and the chamber being hermetically sealed. The electrode within the chamber can be placed in electrical communication with an exterior electrical component by way of the electrically conductive material in the passage.

Abstract: A cascaded photovoltaic/thermophotovoltaic energy conversion apparatus, a cascaded thermophotovoltaic energy conversion apparatus, and a method for forming the apparatuses are provided. The cascaded photovoltaic/thermophotovoltauc apparatus includes a photovoltaic device that receives solar radiation on an upper surface thereof and produces a first electric current output and a thermal radiation output, and a thermophotovoltaic device disposed a predetermined distance below a lower surface of the photovoltaic device, the thermophotovoltaic device receiving the thermal radiation output and converting the received thermal radiation output into a second electric current output.

Abstract: The invention relates to MEMS devices. In one embodiment, a micro-electromechanical system (MEMS) device comprises a resonator element comprising a semiconducting material, and at least one trench formed in the resonator element and filled with a material comprising oxide. Further embodiments comprise additional devices, systems and methods.

Abstract: The thermoelectric detector consists of an absorber structure supported by two electrically connected beams made of thermoelectric materials such as polysilicon, polysilicon/germanium, bismuth-telluride, skutterrides, superlattice structures, nano-composites and other materials. One end of the thermoelectric beam connects to the absorber structure; the other end connects to the substrate. Infrared radiation incident on the absorber heats up the absorber, resulting in a temperature gradient along the length of the thermoelectric legs, and generating an electrical voltage. The detector arrays are fabricated using micromachining process. The absorber structure is formed over a sacrificial material that is removed at the end of the processing, leaving the detector suspended and thermally isolated. The sacrificial processing method enables the production of small pixel thermoelectric detectors in large two-dimensional arrays with high sensitivity.

Abstract: A microelectronic package, a method of forming the package and a system incorporating the package. The package includes a substrate; a die bonded to the substrate; and a thermal sensor connected to the substrate.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: A small infrared sensor has a wide infrared light-receiving area (viewing angle), high electromagnetic shielding characteristics, and excellent electromagnetic-wave resistance characteristics. In the infrared sensor, supporting portions are disposed at four corners of a substantially rectangular opening in a package. The supporting portions support an optical filter, disposed so as to cover the opening, at positions that are lower than an upper end of an inner peripheral wall defining the opening. While the optical filter is supported by the supporting portions as a result of inserting a portion of a surface side of the optical filter facing the supporting portions into the opening, the optical filter is secured to the package. The optical filter and the package are joined and secured, and electrically connected to each other through a conductive adhesive.

Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.

Abstract: There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.

Abstract: A sensing apparatus includes a holding substrate, a sensing chip and a protection layer. The sensing chip is mounted on the holding substrate and electrically connected to the holding substrate. The sensing chip has a sensing region and a non-sensing region other than the sensing region. The sensing region senses image data of an object and thus generates a sensed signal outputted to the holding substrate. The protection layer is formed by a packaging material and is simultaneously processed and integrally formed to cover the sensing region and the non-sensing region of the sensing chip and the holding substrate. The protection layer has an exposed upper surface, which has one portion serving as a sensing surface in contact with the object. The entire protection layer is composed of the same material.

Abstract: The invention discloses a novel flexible, modular fabrication method for integrated high aspect ratio single crystal silicon microstructures designed and manufactured in a post conventional CMOS process (Post-CMOS). The method involves the standard circuits formation, the electrical isolation trenched etching and refilling, backside etching, interconnection formation, and structure releasing. Further, a method of tailoring the trench profile for refill the trench fully without void is also disclosed.

Abstract: A system that facilitates precise inter-chip alignment. The system includes a first integrated circuit chip, whose surface has etch pit wells. The system also includes a second integrated circuit chip, whose surface has corresponding etch pit wells that mate with the etch pit wells of the first integrated circuit chip. Spherical balls are placed in the etch pit wells of the first integrated circuit chip such that when the corresponding etch pit wells of the second integrated circuit chip are substantially aligned with the spherical balls, the spherical balls mate with the etch well pits of the second integrated circuit chip, thereby precisely aligning the first integrated circuit chip with the second integrated circuit chip.

Abstract: A near-field energy conversion structure and method of assembling the same, utilizing a sub-micrometer “near field” gap between juxtaposed photocell infrared radiation receiver and heat emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure.

Abstract: The invention relates to a method for producing Peltier modules, each of which comprises several Peltier elements that are arranged between at least two substrates. The substrates are made of an electrically insulating material at least on the sides facing the Peltier elements while being provided with contact areas on said surfaces. The contact areas, to which the Peltier elements are connected by means of terminal sure during the production process, are formed by metallic areas.

Abstract: A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the semiconductor device and the contactor board are in physical contact. A continuous electrically conductive path is formed with electrically conductive elements involving both the semiconductor device and the contactor board. A complete electrical circuit involving both the semiconductor device and the contactor board is formed only when the relative orientation of the semiconductor device and the contactor board have predetermined relationship and the electrically conductive elements of the two boards are in good physical contact.

Abstract: In a method for producing a sensor arrangement and the resulting sensor arrangement, a sensor is provided on or in a chip and the chip is covered with a protective cover, the cover being an interface between the sensor and the environment. An adhesive layer is provided between the chip and the protective cover, the adhesive layer alone or together with the protective cover being an interface between the sensor and the environment. The protective cover and/or the adhesive layer may have a channel formed therein, the channel functioning as the reception channel for a sensor. In an alternative embodiment, the protective cover placed on a wafer with several chips, and the wafer is cut up to produce the individual chips with the protective cover. Thus, a sensor arrangement may have the protective cover applied to the individual chip after the chip is cut from the wafer, or the protective cover may be applied to the wafer, and the wafer and cover are then cut up into the individual chips and corresponding covers.

Abstract: A sensor device for sensing air flow speed at the exterior of an aircraft, comprising a substrate having an upper side on which is mounted a diaphragm over an aperture or recess in the substrate, the diaphragm being thermally and electrically insulative, and mounting on its upper surface a heating element comprising a layer of resistive material, and wherein electrical connections to the heating element are buried in the diaphragm and/or the substrate, and provide electrical terminals at the lower side of the substrate. The heating element is exposed to the environment, but the remaining electrical parts of the device are not exposed.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Method of forming a microelectronic package using control of die and substrate differential expansions. The method includes: providing a die-substrate combination including a substrate, a die disposed on the substrate, and plurality of solder paste disposed between the die and the substrate; reflowing the solder paste by exposing the die-substrate combination to temperatures changes including heating the die-substrate combination to liquefy the solder paste, and cooling down the die-substrate combination until the solder paste has solidified to form solder joints to yield the package; and controlling an expansion of the die and the substrate at least during cooling down to mitigate a relative difference in volumetric strain between the die and the substrate. Controlling may comprise exposing the die-substrate combination to pressure changes at least during cooling down.

Abstract: A MEMS device includes a P-N device formed on a silicon pin, which is connected to a silicon sub-assembly, and where the P-N device is formed on a silicon substrate that is used to make the silicon pin before it is embedded into a first glass wafer. In one embodiment, forming the P-N device includes selectively diffusing an impurity into the silicon pin and configuring the P-N device to operate as a temperature sensor.

Abstract: A packaging structure and method for a light emitting diode is provided. The present invention uses flip-chip and eutectic bonding technology to attach a LED to a thermal and electrical conducting substrate. The flip-chip packaging structure comprises a thermal and electrical conducting substrate having an insulating layer formed in an appropriate area on the top surface of the substrate and a bonding pad formed on top of the insulating layer; and a LED reversed in a flip-chip style and joined to the substrate by eutectic bonding. A first electrode of the LED is eutectically bonded to an appropriate area on the top surface of the substrate via a eutectic layer, while a second electrode of the LED is electrically connected to the bonding pad.

Abstract: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.

Abstract: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.

Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.

Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.