Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Abstract: A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

Abstract: Disclosed is a display panel including: a flexible substrate; a buffer layer disposed on the flexible substrate; a pixel disposed on the buffer layer and comprising a thin film transistor and an image device connected to the thin film transistor; a barrier layer disposed on the flexible substrate to protect the pixel from a substance from the flexible substrate; and a diffusion prevention layer disposed between the barrier layer and the buffer layer and configured to prevent hydrogen generated from the barrier layer from being diffused into the thin film transistor.

Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Abstract: A method of removing a dummy gate dielectric layer is provided. Firstly a first plasma containing F is utilized to remove the dummy dielectric layer which contains Si and O. Then a second plasma containing H2 is utilized to remove fluorine compound on the surface of the semiconductor substrate. Since the fluorine residue formed after the first plasma treatment reacts with the second plasma to form a gaseous product HF, the fluorine element can be taken away from the semiconductor device with the HF, which prevents inversion layer offset and gate current leakage occurred in the subsequent processing steps due to the fluorine element.

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region, forming a first gate structure in the low-density region and a second gate structure in the high-density region, form an etch stop layer on the first and second gate structures, and forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate. The method further includes performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure, performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure, and performing a third CMP process to completely remove the etch stop layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over the fin structure; source/drain regions over the substrate and disposed on opposing sides of the gate stack; a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped; and a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide.

Abstract: A conductive contact pattern is formed on a surface of solar cell by forming a thin conductive layer over at least one lower layer of the solar cell, and ablating a majority of the thin conductive layer using a laser beam, thereby leaving behind the conductive contact pattern. The laser has a top-hat profile, enabling precision while scanning and ablating the thin layer across the surface. Heterocontact patterns are also similarly formed.

Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The etching chemistries are different for each of the two etching steps. The first chemistry used to etch the top portion of the electrode is more selective with respect to the conductive material of the top electrode, thereby reducing unwanted erosion of the photoresist and hard mask layers. The second chemistry is less corrosive than the first chemistry and does not damage the layers underlying the top electrode, such as those included in the magnetic tunnel junction.

Abstract: A horizontal electric field mode liquid crystal display device having a novel electrode structure, and a manufacturing method thereof are provided. The liquid crystal display device includes a first substrate having an insulating surface; a first conductive film and a second conductive film over the insulating surface; a first insulating film over the first conductive film; a second insulating film over the second conductive film; a second substrate facing the first substrate; and a liquid crystal layer positioned between the first substrate and the second substrate. Part of the first conductive film exists also on a side portion of the first insulating film, and part of the second conductive film exists also on a side portion of the second insulating film. The liquid crystal layer includes liquid crystal exhibiting a blue phase.

Abstract: A plasma etching method for plasma etching a film to be etched to a size smaller than a prescribed size using a mask patterned to the prescribed size performs etching on the film to be etched to the size smaller than the prescribed size while forming a protection film on side walls of the film to be etched.

Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Abstract: A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The multiple patterning method also includes forming a first mask film on the sacrificial film; and forming a second mask film for subsequently forming a certain structure to protect the subsequently formed mask structures on the first mask film. Further, the multiple patterning method includes forming first mask structures and second mask structures by etching the second mask film, the first mask film, and the sacrificial film.

Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

Abstract: A manufacturing method of a low temperature polycrystalline silicon thin film and a manufacturing method of a thin film transistor are provided. The manufacturing method of the low temperature polycrystalline silicon thin film comprises: forming an amorphous silicon thin film on a substrate; and performing a rapid thermal annealing (RTA) process on the amorphous silicon thin film for several times at a predetermined temperature to form the low temperature polycrystalline silicon thin film, wherein the predetermined temperature is lower than a conventional RTA crystallization temperature.

Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first dummy gate on the semiconductor substrate in the first region and a device layer on the semiconductor substrate in the second region. The method also includes forming a dielectric layer on of the first dummy gate and the device layer; and removing the first dummy gate to form a first trench. Further, the method includes forming a first metal layer on the first trench and the surfaces of the dielectric layer and the device layer; and performing a first planarization process onto the first metal layer using a polishing slurry having a first protective agent to form a first gate electrode in the first trench and form a protective layer on the device layer preventing the device layer being damaged during the first planarization process.

Abstract: A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.

Abstract: A method of forming a pattern of a semiconductor device includes providing a substrate, forming a photoresist layer by coating a resist composition including an acid generator and a first resin, the first resin having an acid-labile group, exposing the photoresist layer, forming a photoresist pattern by negatively developing the photoresist layer using a developing solution including an organic solvent, coating a capping composition including a second resin and the organic solvent on the substrate having the photoresist pattern formed thereon, and attaching a capping layer on upper and side surfaces of the photoresist pattern, by baking the capping composition and developing the capping composition using the developing solution including the organic solvent.

Abstract: One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.

Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.

Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Abstract: Methods of polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch are described. In an example, a method of forming a three-dimensional gate structure includes performing a main plasma etch on a masked polysilicon layer formed over a semiconductor fin. The method also includes, subsequently, performing a plasma over etch on the masked polysilicon layer based on a plasma generated from gaseous composition including hydrogen gas (H2).

Abstract: There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask pattern by etchback of a deposited second film, removing the first mask pattern, and forming a second mask pattern composed of the first sidewall films and second sidewall films defined by etchback of a deposited third film. It is possible to form a stripe pattern with the line width and the line space thereof having the same sizes and at a pitch the same as the minimum process size determined by the photolithographic performance, thereby enabling fabrication of a semiconductor device with a high degree of integration.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.

Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

Abstract: A image forming apparatus having a plurality of applications, which is capable of properly reproducing settings desired by each user, and is thereby improved in user-friendliness. A storage controller stores a file with which first print settings can be associated. The storage controller stores second print settings in a manner associated with a user. An operation controller selects a file stored in association with the first print settings according to an instruction from a user who has logged into the image forming apparatus. A CPU executes print processing according to the first print settings when the first print settings are associated with the selected file, and on the other hand executes print processing according to the second print settings when the first print settings are not associated with the selected file.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A semiconductor device includes a substrate and a plurality of fin structures. A first fin structure and a second fin structure are spaced at a distance D1. A first dummy fin structure is adjacent to the first fin structure, and a second dummy fin structure is adjacent to the second fin structure. The device further includes an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures. The fin structures are arranged such that a distance D2 between the first fin structure and the first dummy fin structure is greater than the distance D1.

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Abstract: An image sensor pixel array includes a photoelectric conversion unit comprising a photoelectron accumulation region of n-type in a substrate of p-type and vertically below a gate electrode of a transistor. A light guide transmits a light of red or green or yellow color across the gate electrode to the photoelectron accumulation region. The gate electrode may be made thinner by a wet etch. An etchant for thinning the gate electrode may be introduced through an opening in an insulating film on the substrate. The light guide may be formed in the opening after the thinning. An anti-reflection stack may be formed at a bottom of the opening prior to forming the light guide.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Abstract: According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.

Abstract: A tap cell includes a well region and a well pickup region of the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is coupled to the VDD power rail, and a second one of the first and second capacitor plates is coupled to the VSS power rail.

Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.

Abstract: In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.

Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.

Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel

Abstract: A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to a D.C. power ranging between 500 and 1,000 W. An insulated gate comprising such an aluminum titanium nitride layer.

Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.

Abstract: According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased.