Insulated Gate Formation Patents (Class 438/585)
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Patent number: 9018084Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.Type: GrantFiled: September 9, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Ryan M. Martin, Jeffrey W. Sleight
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Patent number: 9018629Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.Type: GrantFiled: October 5, 2012Date of Patent: April 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sachiaki Tezuka, Atsuo Isobe, Takehisa Hatano, Kazuya Hanaoka
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Patent number: 9012317Abstract: A method is provided for forming a flash memory. The method includes providing a semiconductor substrate; and forming a first dielectric layer. The method also includes forming a first semiconductor layer on a surface of the first dielectric layer; and performing an ion implantation onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate. Further, the method includes performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer; and forming a second dielectric layer having an opening exposing the position of the first select gate. Further, the method also includes forming a second semiconductor layer on the second dielectric layer; and forming a flash cell and a select gate structure.Type: GrantFiled: February 28, 2014Date of Patent: April 21, 2015Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventor: Yong Chen
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Patent number: 9006110Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.Type: GrantFiled: November 8, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Chien-Ying Sun, En-Chiuan Liou, Jia-Rong Wu, Ching-Wen Hung
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Patent number: 9006089Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.Type: GrantFiled: October 27, 2014Date of Patent: April 14, 2015Assignee: SK Hynix Inc.Inventor: Sung-Wook Jung
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Patent number: 9006088Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnOx passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnOx , GeSnN or GeSnON passivation layer.Type: GrantFiled: June 14, 2013Date of Patent: April 14, 2015Assignee: Tsinghua UniversityInventors: Mei Zhao, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 9006090Abstract: A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced.Type: GrantFiled: September 6, 2013Date of Patent: April 14, 2015Assignee: Mosel Vitelic Inc.Inventor: Richard Lai
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Patent number: 8999794Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.Type: GrantFiled: July 14, 2011Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ziwei Fang, Ying Zhang, Jeff J. Xu
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Patent number: 8999842Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: GrantFiled: July 21, 2014Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8999793Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.Type: GrantFiled: June 17, 2014Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
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Patent number: 8999851Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.Type: GrantFiled: December 9, 2008Date of Patent: April 7, 2015Assignee: OneD Material LLCInventors: Francisco Leon, Francesco Lemmi, Jeffrey Miller, David Dutton, David P. Stumbo
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Publication number: 20150093887Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.Type: ApplicationFiled: April 15, 2014Publication date: April 2, 2015Applicant: GLOBALFOUNDRIES, INC.Inventors: Bin Yang, Shurong Liang, Kristina Young-Fisher, Kevin Kashefi, Amol Joshi, Salil Mujumdar, Abhijit Pethe, Albert Lee, Ashish Bodke
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Patent number: 8993417Abstract: An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a first annealing process, the first annealing process including a first wet anneal, the first wet anneal removing impurities from the isolation region; a second wet anneal, the second wet anneal forming silanol in the isolation region; and a first dry anneal, the first dry anneal dehydrating the isolation region. In an embodiment, the first annealing process is followed by a chemical mechanical planarization (CMP) process, an etching process, and a second annealing process for the isolation region.Type: GrantFiled: June 28, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Shiang-Rung Tsai
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Patent number: 8994125Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.Type: GrantFiled: August 20, 2012Date of Patent: March 31, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Kenshi Kanegae
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Patent number: 8987827Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.Type: GrantFiled: May 31, 2013Date of Patent: March 24, 2015Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GLOBALFOUNDRIES, Inc.Inventors: Pietro Montanini, Raymond Joy, Marta Mottura, Henry K. Utomo
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Patent number: 8987125Abstract: The present invention relates to a method for manufacturing a heterojunction semiconductor device including an AlGaN layer, the method including the steps of (a) forming a dummy electrode in a region where a gate electrode is arranged on the AlGaN layer, (b) depositing a dielectric film on the AlGaN layer by exposing side surfaces of the dummy electrode, using a device having anisotropy, (c) forming an opening in the dielectric film by removing the dummy electrode, and (d) forming the gate electrode that extends from inside the opening onto the dielectric film in a vicinity of the opening.Type: GrantFiled: June 5, 2013Date of Patent: March 24, 2015Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Okazaki, Takuma Nanjo, Yosuke Suzuki, Akifumi Imai, Muneyoshi Suita, Eiji Yagyu
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Publication number: 20150076618Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.Type: ApplicationFiled: September 19, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Ran Yan, Nicolas Sassiat, Ralf Richter, Jan Hoentschel
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Publication number: 20150079775Abstract: Systems and methods are provided for fabricating semiconductor devices. For example, a substrate is provided. A polymer layer is formed on the substrate. An oxygen-based plasma is applied to remove the polymer layer. An oxidizing solution is applied to generate a dielectric layer. A conductive layer is formed on the dielectric layer for fabricating semiconductor devices.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventor: SHAO-JYUN WU
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Patent number: 8980706Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region.Type: GrantFiled: February 12, 2009Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Fang Wen Tsai, Chi-Chun Chen
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Publication number: 20150069475Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
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Publication number: 20150060958Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shih-Hung Chen, Erh-Kun Lai
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Publication number: 20150062996Abstract: An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Yanxiang LIU, Min-hwa CHI, Anurag MITTAL
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Publication number: 20150061027Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Publication number: 20150064891Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Publication number: 20150061037Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: QUALCOMM IncorporatedInventors: Ming Cai, Samit Sengupta, Chock Hing Gan, PR Chidambaram
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Patent number: 8969187Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.Type: GrantFiled: April 9, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Dechao Guo, Wilfried E. A. Haensch, Shu-Jen Han, Chung-Hsun Lin
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Publication number: 20150056795Abstract: A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region. A sacrificial material film that has an etch selectivity that is the same as an etch selectivity of the gate electrode material film is formed. The sacrificial material film is planarized until a top surface of the gate electrode material film is exposed. The stepped portion is reduced by removing an exposed portion of the gate electrode material film.Type: ApplicationFiled: July 29, 2014Publication date: February 26, 2015Inventors: Bo-kyeong Kang, Bo-un Yoon, Il-young Yoon, Jae-kwang Choi, Ho-young Kim, Se-jung Park, Jae-seok Kim
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Patent number: 8962412Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.Type: GrantFiled: August 11, 2014Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kerber, Christian Lavoie
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Patent number: 8962494Abstract: The present invention provides method of manufacturing dual gate oxide devices. The method comprises coating photoresist on the substrate which is deposited by an oxide thin film; removing some of the photoresist by exposure and development to divide the oxide thin film into a first area to be etched and a second area coated by the remained photoresist; coating RELACS material on the remained photoresist and heating to form a protective film based on the crosslinking reaction between the RELACS material and the high molecular compounds in the photoresist; performing UV radiation to strengthen and cure the protective film; removing the oxide thin film in the first area by etching and removing the remained photoresist; and depositing again an oxide firm to form an oxide layer of different thickness in the first area and the second area so as to form a dual gate oxide structure.Type: GrantFiled: September 30, 2013Date of Patent: February 24, 2015Assignee: Shanghai Huali Microelectronics CorporationInventors: Jun Huang, Zhibiao Mao, Ermin Chong
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Publication number: 20150050801Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.Type: ApplicationFiled: November 20, 2013Publication date: February 19, 2015Applicant: Shanghai Huali Microelectronics CorporationInventors: Jun HUANG, ZhiBiao MAO, QuanBo LI, ZhiFeng GAN, RunLing LI
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Publication number: 20150048437Abstract: According to one embodiment, a semiconductor memory device includes an insulating film with a recess formed in an upper surface, and a conductive film provided on the insulating film and containing silicon, carbon and an impurity serving as an acceptor or donor for silicon. Carbon concentration of a first portion of the conductive film in contact with the insulating film is lower than carbon concentration of a second portion of the conductive film located in the recess and being equidistant from the insulating film placed on both sides thereof.Type: ApplicationFiled: December 4, 2013Publication date: February 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takuo OHASHI, Fumiki AlSO
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Publication number: 20150048456Abstract: A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and completely surrounding at least one of the two or more active regions. A second set of dummy blocks are over the substrate and farther from the at least one active region surrounded by the first set of dummy blocks than the dummy blocks of the first set of dummy blocks. Each of the dummy blocks of the first set of dummy blocks has individual surface areas, each of the dummy blocks of the second set of dummy blocks has individual surface areas, and the individual surface areas of each of the dummy blocks of the second set of dummy blocks is larger than the individual surface areas of each of the dummy blocks of the first set of dummy blocks.Type: ApplicationFiled: September 25, 2014Publication date: February 19, 2015Inventors: Harry-Hak-Lay CHUANG, Cheng-Cheng KUO
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Patent number: 8956964Abstract: Semiconductor devices and fabrication methods are provided. A fin can be formed on a semiconductor substrate, a gate can be formed across the fin, and sidewall spacers can be formed across the fin on both sides of the gate. A dummy contact can be formed across the fin and on each of the both sides of the sidewall spacers. After forming an interlayer dielectric layer on the semiconductor substrate, the dummy contact can be removed to form a contact trench. The dummy contact is made of a material having an etch selectivity sufficiently higher than the fin such that the removing of the dummy contact generates substantially no damage to the fin. A conductive material can be filled in the contact trench to form a trench metal contact.Type: GrantFiled: November 12, 2013Date of Patent: February 17, 2015Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xinpeng Wang, Steven Zhang
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Publication number: 20150041912Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.Type: ApplicationFiled: December 19, 2013Publication date: February 12, 2015Applicant: Intermolecular, Inc.Inventors: Khaled Ahmed, Frank Greer
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Patent number: 8951901Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.Type: GrantFiled: July 22, 2011Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
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Patent number: 8951902Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.Type: GrantFiled: January 31, 2012Date of Patent: February 10, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
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Publication number: 20150034971Abstract: [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. [ Solution Means] A semiconductor device 1 has an MIS structure including an SiC epitaxial layer 3, a gate insulating film 9 and a gate electrode 10 formed on the gate insulating film 9. A gate insulating film 9 includes a silicon oxide film in contact with the SiC epitaxial layer 3. In the MIS structure, an area density QM of positive mobile ions in the gate insulating film 9 is made no more than 1×1012 cm?2.Type: ApplicationFiled: February 22, 2013Publication date: February 5, 2015Inventors: Heiji Watanabe, Takayoshi Sshimura, Takuji Hosoi, Shuhei Mitani, Yuki Nakano, Ryota Nakamura, Takashi Nakamura
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Publication number: 20150034957Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
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Publication number: 20150034960Abstract: A method of manufacturing a semiconductor device is provided as a semiconductor device manufacturing method that permits an opening to be formed in a good shape in a resist film. This manufacturing method is a semiconductor device manufacturing method having: a step of forming an insulating film 22 of any one of silicon nitride, silicon oxide, and silicon oxynitride, on a nitride semiconductor layer 20 or on a silicon carbide layer; a step of performing a treatment of oxidation or nitridation for a surface of the insulating film 22; a step of forming an EB resist film 46 on the insulating film 22, after completion of the treatment of oxidation or nitridation; and a step of irradiating the EB resist film 46 with an electron beam to effect exposure.Type: ApplicationFiled: May 23, 2014Publication date: February 5, 2015Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Tsutomu KOMATANI
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Fabricating method of semiconductor device and semiconductor device fabricated using the same method
Patent number: 8946069Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.Type: GrantFiled: December 23, 2013Date of Patent: February 3, 2015Assignee: Samsung Electronics Co. Ltd.Inventors: Jin-Wook Lee, Myeong-Cheol Kim, Sang-Min Lee, Young-Ju Park, Hyung-Yong Kim, Myung-Hoon Jung -
Patent number: 8946007Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.Type: GrantFiled: February 7, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
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Patent number: 8946035Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.Type: GrantFiled: September 27, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
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Patent number: 8946097Abstract: A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer.Type: GrantFiled: April 11, 2013Date of Patent: February 3, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8946026Abstract: A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.Type: GrantFiled: September 21, 2011Date of Patent: February 3, 2015Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Sukhun Choi, Boun Yoon, Jae-Jik Baek, Byung-Kwon Cho
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Patent number: 8940597Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.Type: GrantFiled: March 11, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Jung Hsu, Gin-Chen Huang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20150024578Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.Type: ApplicationFiled: July 18, 2013Publication date: January 22, 2015Inventors: Johannes von Kluge, Berthold Reimer
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Publication number: 20150021607Abstract: A thin film transistor substrate includes: a polymer substrate, an oxide transparent electrode layer (TCO) formed on the polymer substrate, a barrier layer formed on the oxide transparent electrode layer, and a semiconductor layer formed on the barrier layer, in which the semiconductor layer is polysilicon. The polysilicon thin film transistor provides an oxide transparent electrode layer (TCO) which absorbs heat energy and light generated during a process of manufacturing the polysilicon thin film transistor to prevent a damage of the substrate using a polymer material.Type: ApplicationFiled: November 22, 2013Publication date: January 22, 2015Applicant: Samsung Display Co., Ltd.Inventors: Young Sik Yoon, Youn Joon Kim, Seung Peom Noh, Sang Jo Lee, Ji Won Han
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Patent number: 8932945Abstract: A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.Type: GrantFiled: July 9, 2012Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Hong Syue, Chung-Chun Ho, Pu-Fang Chen, Shiang-Bau Wang
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Patent number: 8932946Abstract: According to one or more embodiments of the present invention, a method for driving a power semiconductor device that has a source electrode, a drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, a plurality of gate electrodes formed within the semiconductor layer, and a plurality of conductive layers that are formed between the gate electrodes and the drain electrode and in electrical communication with the gate electrodes. The method comprises providing a first electric potential to the source electrode, providing a second electric potential to the drain electrode, providing a third electric potential to the gate electrodes, providing a first electric potential to at least one of the conductive layers, and providing a third electric potential to at least another one of the conductive layers.Type: GrantFiled: February 19, 2014Date of Patent: January 13, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Wataru Saito
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Patent number: 8927406Abstract: A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer around the dummy gate, and depositing and planarizing a dielectric layer. The method further includes selectively removing the expanding layer, and removing the dummy gate.Type: GrantFiled: January 10, 2013Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko