Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]—[H]}/2?1.0×1021 cm?3.

Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.

Abstract: A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.

Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.

Abstract: Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used.

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

Abstract: A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.

Abstract: An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.

Abstract: A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.

Abstract: An integrated circuit device comprises a common-gated dual-oxide MOSFET including a protective device and a MOSFET. A common gate electrode serves as a gate electrode of the protective device and as a gate of the MOSFET. The protective device comprises a first gate dielectric having a first thickness over a first channel region and the MOSFET comprises a second gate dielectric thicker than the first gate dielectric over a second channel region. During a plasma process, a first current can flow through the first dielectric that is higher than a second current through the second dielectric.

Abstract: A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.

Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.

Abstract: A method of improving the yield of semiconductor devices includes implanting ions into a NMOS gate. A layer of PEOX film is deposited upon the gate. A layer of LTO film is deposited upon the PEOX film. The method solves the problems of ions implanted on the NMOS gate diffusing to the structure of the PMOS gate due to the high temperature annealing process which impairs the electrical characteristic of the PMOS; the aggregation and precipitation of the ions to the surface of the gate due to the porosity of PEOX film, which impairs the active area of NMOS in the subsequent etching process; that the LTO film is easily influenced by the lower layer film and is affected by the speed of surface atom diffusion of the lower layer thereby avoiding differences in thickness of LTO film deposited on NMOS and PMOS.

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract: An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.

Abstract: Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.

Abstract: A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.

Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer ?-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract: Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices.

Abstract: Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form the gate conductor.

Abstract: A method for forming a semiconductor device includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode, at least two hard mask (HM) layers over the gate electrode, and a spacer abutting a side wall of the gate electrode and the at least two hard mask layers. The method further comprises forming a contact etch stop layer (CESL) over the gate structure, exposing at least one of the HM layers after forming the CESL, and removing the exposed at least one of the HM layers.

Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract: A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface.

Abstract: Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided.

Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Abstract: A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract: According to one embodiment, a pattern forming method is disclosed. A resist pattern having a top surface is formed pattern on a substrate. A coating film having a first thickness distribution is formed on the substrate. The coating film covers the resist pattern. The coating film is thinned to expose the top surface of the resist pattern. The first thickness distribution is changed into a second thickness distribution which is more uniform than the first thickness distribution. The resist pattern is removed without removing the coating film. A pattern is formed in the substrate by processing the substrate by using the coating film as a mask.

Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Abstract: According to the present invention, there is provided a process for producing a transistor having a high precision and a high quality with a high yield by selectively etching a natural silicon oxide film, and further by selectively etching a dummy gate made of silicon. The present invention relates to a process for producing a transistor using a structural body which includes a substrate, and a dummy gate laminate formed by laminating at least a high dielectric material film and a dummy gate made of silicon having a natural silicon oxide film on a surface thereof, a side wall disposed to cover a side surface of the laminate and an interlayer insulating film disposed to cover the side wall which are provided on the substrate, said process including an etching step using a specific etching solution and thereby replacing the dummy gate with an aluminum metal gate.

Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.

Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.

Abstract: A wafer transfer assembly and method of using the assembly to transfer device wafers between processing tools in a manufacturing process are described herein. The assembly comprises a wafer transfer disk, an end effector configured to receive and support the wafer transfer disk, and an elongated handle extending from the end effector. The wafer transfer disk comprises a wafer-engaging surface configured to support a debonded device wafer placed on the wafer transfer assembly with the device surface adjacent the wafer-engaging surface. The wafer-engaging surface has non-stick properties, and yields a low bonding strength interface between the wafer-engaging surface and device surface. The resulting transfer stack can be transported to other processing tools for additional processing of the debonded device wafer, followed by separating the debonded device wafer and the wafer transfer disk without damaging the device wafer.