Abstract: Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.

Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.

Abstract: To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. A process for fabricating the package includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad.

Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Abstract: Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material.

Abstract: A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.

Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.

Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.

Abstract: A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads.

Abstract: A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.

Abstract: The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.

Abstract: An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.

Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract: Methods and structure for adapting MEMS structures to form electrical interconnections for integrated circuits. A first portion and a second portion of the metal conductor, which can be electrically isolated within a CMOS IC device, can be etched to form an unetched portion of the metal conductor. The MEMS device can be patterned, from a MEMS layer formed overlying the metal conductor, via a plasma etching process, during which the unetched portion of the metal conductor is protected from the plasma. The metal conductor can be electrically coupled to the CMOS IC device via a conductive jumper or the like. Furthermore, the integrated CMOS-MEMS device can include a MEMS device coupled to a CMOS IC device via an electrically isolated metal conductor within the CMOS IC device. Also, the metal conductor can be electrically coupled to the substrate of the CMOS IC device via a conductive jumper.

Abstract: An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

Abstract: An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect.

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.

Abstract: A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.

Abstract: A method of manufacturing a semiconductor device, includes: preparing a semiconductor IC chip and an external electrode terminal which is positioned away from the semiconductor IC chip, wherein the semiconductor IC chip has first and second electrode pads thereon, the second electrode pad being positioned between the first electrode pad and the external electrode terminal; connecting the first electrode pad and the external electrode terminal by a loop-like wire; and pressing a portion of the loop-like wire toward the semiconductor IC chip, thereby connecting the portion of the loop-like wire with the second electrode pad.

Abstract: An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a carrier top side; mounting an integrated circuit over the carrier top side; attaching a bottom attachment directly on the integrated circuit; dragging a sandwich connector from the bottom attachment, the sandwich connector having a connector diameter; and attaching a top attachment directly on the sandwich connector, the top attachment wider than the bottom attachment.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.

Abstract: A semiconductor device (10) is made by mounting the bottom surfaces (31, 44, 54) of a semiconductor die (14) and a lead (15, 17) on a tape (12) and over a hole (19) in the tape. A vacuum is drawn through the hole to secure the die in place when the lead's top surface (43) is wirebonded to a top surface (32) of the semiconductor die. A molding material (49) is formed to encapsulate the top surface of the semiconductor die and to expose its bottom surface.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.

Abstract: A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved.

Abstract: A lead frame assembly for an integrated circuit package includes a lead frame, a die, first and second information signal-carrying bond wires, first and second ground bond wires, and first and second ground down bond wires. Each ground bond wire shares a die pad with one of the ground down bond wires.

Abstract: In accordance with the present invention, there is provided a routable substrate that may be used, for example, in relation to the manufacture of Dual and Quad Flat No-Lead (DFN/QFN) style semiconductor packages as a substrate or interposer of such packages. The method of fabricating the substrate effectively removes metal from the saw streets and provides a more stable surface structure for wire bonding. The substrate fabrication method also utilizes existing etching techniques which are implemented in a prescribed sequence to achieve no metal in the saw streets and to completely electrically isolated features. Further, the substrate fabrication method includes a molding step intended to replace pressure sensitive adhesive tapes.

Abstract: A bonding connection between a bonding wire and a power semiconductor chip is disclosed. The power semiconductor chip has a semiconductor body arranged in which is an active cell region with a multiplicity of cells arranged one following the other in a lateral direction and connected electrically in parallel. The semiconductor body has a surface portion arranged above the active cell region in a vertical direction perpendicular to the lateral direction. Applied to the surface portion is a metallization layer onto which a bonding wire is bonded. The bonding wire comprises an alloy containing at least 99% by weight aluminum and at least one further alloying constituent. The aluminum has a grain structure with a mean grain size which is less than 2 ?m.

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract: An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.

Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: There is provided a semiconductor device and a manufacturing method therefor, the semiconductor device requiring flip-chip mounting of a fine pitch electrode, wherein the fine electrode is easily manufactured, resin sealing is not required, and reliability can be improved. In the semiconductor device, one or more LSI chips (1), having an insulating layer (3) surface and an electrode (2) surface on one side, and a substrate (4), having an insulating layer (6) surface and an electrode (5) surface on one side, are bonded by having surfaces of the electrodes and surfaces of the insulating layers face each other via a bonding layer (7) made in a thin film form, in a region excluding the surfaces of the electrodes (2, 5) and the surfaces of the insulating layers (3, 6) in areas surrounding the electrodes.