Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.

Abstract: In a method of bonding a first bump on a surface of a first member and a second bump on a surface of a second member, a tip portion of the first bump is provided with a projection having a hardness greater than a hardness of each of the first and second bumps. The first and second members are positioned with respect to each other such that the first and second bumps face each other. The tip portion of the first bump is brought into contact with a tip portion of the second bump by sticking the projection into the tip portion of the second bump.

Abstract: A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package.

Abstract: An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create a design restriction that has the potential to limit cooling capability.

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact.

Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.

Abstract: A light emitting apparatus includes a semiconductor layer having an electrode with two traces physically separated from one another. The light emitting apparatus further includes a wire bond electrically connecting the two traces.

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract: A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of stacking the semiconductor substrates in a stacked array with aligned vias; threading a wire through the aligned vias; and forming a plurality of electrical connections between the wire and the contacts on the semiconductor substrates.

Abstract: A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.

Abstract: Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected to common wiring 3p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3a of package substrate 3, and the back surface. Even if the land part of plural lines is formed covering the perimeter of the back surface, electrolysis plating can be performed to the all land parts. As a result, electrolysis plating can be performed to a wiring, aiming at the increasing of pin count of a semiconductor device.

Abstract: A method of manufacturing a semiconductor device, includes: preparing a semiconductor IC chip and an external electrode terminal which is positioned away from the semiconductor IC chip, wherein the semiconductor IC chip has first and second electrode pads thereon, the second electrode pad being positioned between the first electrode pad and the external electrode terminal; connecting the first electrode pad and the external electrode terminal by a loop-like wire; and pressing a portion of the loop-like wire toward the semiconductor IC chip, thereby connecting the portion of the loop-like wire with the second electrode pad.

Abstract: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Abstract: A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.

Abstract: A manufacturing method for a semiconductor device including: determining pattern dependency of a radiation factor of an element forming surface of one wafer having a predetermined pattern formed on the wafer; determining a heating surface of the wafer, based on the pattern dependency of the radiation factor; holding the one wafer having the determined heating surface and another wafer having a determined heating surface, spaced at a predetermined distance in such a manner that non-heating surfaces of the one wafer and the another wafer oppose to each other; and heating the each heating surface of the one wafer and the another wafer.

Abstract: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 ?m or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Abstract: An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.

Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %?Sb/(Sn+Sb)?48 wt %, 5 wt %?Ag<20 wt %, 3 wt %?Cu<10 wt %, and Ag+Cu?25 wt %.

Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Abstract: An integrated circuit package system comprising: providing a substrate; attaching an integrated circuit die over the substrate; attaching a connector to the integrated circuit die and the substrate; and forming an encapsulant over the substrate, the integrated circuit die, and the connector and minimizing ambient gas deformation of the substrate to keep the connector from touching another connector.

Abstract: It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 ?m in thickness.

Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Abstract: A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.

Abstract: An integrated circuit module comprises a chip, the chip comprising a substrate with a first main area and a second main area, the first main area comprising two half-sets of pads, the chip further comprising an integrated circuit with components and two half-sets of connection lines, the connection lines connecting the components of the integrated circuit to the pads, the integrated circuit further comprising a changeover device, the changeover device having two switching states in order to interchange the electrical assignment between the half-sets of the connection lines and the half-sets of the pads, and a carrier, the carrier comprising contact pieces. The chip is arranged on the carrier with one of the two main areas of the chip facing the carrier and the contact pieces of the carrier are connected to the pads of the chip, wherein one of the two switching states of the changeover device is selected, depending on which of the two main areas of the chip is the area facing the carrier.

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract: Wire bonding method for reducing height of a wire loop in a semiconductor device, including a first bonding step of bonding an initial ball formed at a tip end of a wire onto a first bonding point using a capillary, thereby forming a pressure-bonded ball; a wire pushing step of pushing the wire obliquely downward toward the second bonding point at a plurality of positions by repeating a sequential movement for a plurality of times, the sequential movement including moving of the capillary substantially vertically upward and then obliquely downward toward the second bonding point by a distance shorter than a rising distance that the capillary has moved upward; and a second bonding step of moving the capillary upward and then toward the second bonding point, and bonding the wire onto the second bonding point by pressure-bonding.

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract: A method of manufacturing a semiconductor device is provided. A first bond of a first wire loop is formed. A wire is bonded through a ball to a lead or a chip electrode of a semiconductor chip to form a second bond of the first wire loop and a first bond of a second wire loop. A second bond of the second wire loop is formed. The ball provides a large bonding area, and thus, provides a strong bonding strength.

Abstract: Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

Abstract: A semiconductor device has a first layer pressing portion that is formed by crushing a ball neck formed by bonding an initial ball onto a first layer pad of a first layer semiconductor die and pressing the side of a wire folded onto the crushed ball neck, a first wire extended in the direction of a lead from the first layer pressing portion, and a second wire that is looped from a second layer pad of a second layer semiconductor die toward the first layer pressing portion and joined onto the second layer pad side of the first layer pressing portion. Thereby, the connection of wires is performed at a small number of times of bonding, while reducing damages caused on the semiconductor dies.

Abstract: A wire loop comprises a wire connecting a first bonding point and a second bonding point therethrough, wherein the wire includes a ball bonded to the first bonding point, a neck portion adjacent to the ball and a major portion extending from the neck portion to the second bonding point. The neck portion includes a riser part which extends, from the bonded ball, obliquely upward in a direction toward the second bonding point, and the riser part is formed by a top portion of the ball which has entered an opening of a capillary and been shaped at the time of ball bonding. The riser part is formed by inclining the top portion of the ball, which enters the opening of the capillary at the time of ball bonding, which inclining is done by moving the capillary obliquely upward toward the second bonding point.

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Abstract: After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a semiconductor element 10 is employed in which a gold wire 16 with its one end connected to an electrode terminal of the semiconductor element is extended out to the side surface. A conductive paste 36 containing conductive particles applied over a predetermined length of a transferring wire 30 is transferred to the side surface of the stacked body P so that the gold wires 16 extended out to the side surfaces of the semiconductor elements 10, 10, 10 are connected, thereby forming the side wirings.

Abstract: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.

Abstract: A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

Abstract: Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 ?m, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.