Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.

Abstract: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced.

Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.

Abstract: A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a wireless electronic device mounting the semiconductor device.

Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor substrate; forming a seed layer on the contact hole through electroless plating process; and forming a metal interconnection in the contact hole on the seed layer.

Abstract: In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through the via hole resist mask. Then, the via hole resist mask is removed by an ashing process and a protective film is formed on an underlayer of the insulating film; Thereafter, a trench is formed by etching the insulating film through the trench mask, and the semiconductor substrate is unloaded from the processing chamber after the via hole forming step, the resist mask removing step, the protective film forming step and the trench forming step are completed in the processing chamber.

Abstract: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

Abstract: A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and an adjacent lower copper layer structure. More specifically, the interconnect structure comprises a recess formed in a dielectric layer; a barrier metal lining sidewalls of the recess; a first copper layer within the recess; a second copper layer within the recess; and a metal layer buried between the first copper layer and the second copper layer. The method comprises forming a recess in an interlayer dielectric; forming a first copper layer, a metal layer over the first copper layer and a second copper layer over the metal layer, all within the recess. The metal layer is sandwiched between the first copper layer and the second copper layer within the recess.

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 ?m. The reason is as follows. If the diameter of the mesh hole is less than 75 ?m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 ?m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 ?m. The reason is as follows. If the distance is less than 100 ?m, the solid layer cannot function. If the distance exceeds 2000 ?m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract: Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.

Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.

Abstract: An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.

Abstract: A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer having high viscosity at a lower portion of the through hole in order to seal the lower portion thereof, and forming a through electrode by filling copper in the through hole. There is an effect of efficiently forming a through electrode having a large depth corresponding to the height of stacked semiconductor devices in the system in package. Filling copper in a through hole having a large depth-to-width ratio may be efficiently done by OSP coating, electrolysis copper plating, and electro Cu plating processes.

Abstract: A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a conductive layer and a connecting member. The method includes: forming the semiconductor part on a semiconductor substrate so that a cell portion is provided; forming the conductive layer on the substrate; forming a first resist layer to cover a part of the conductive layer corresponding to the cell portion; etching the conductive layer with the first resist layer as a mask so that a first conductive layer is provided; removing the first resist layer and forming a second conductive layer to cover a surface and an edge of the first conductive layer. The second conductive layer has a Young's modulus equal to or larger than the semiconductor substrate.

Abstract: A semiconductor device includes an interconnection layer provided on a substrate, a first insulating film provided on the substrate, and on the interconnection layer so as to coat the interconnection layer, the first insulating film includes a silicon oxide film, a second insulating film provided on the first insulating film, the second insulating film includes either a silicon oxynitride film or a silicon nitride film, and an insulative coating film provided on the second insulating film.

Abstract: Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

Abstract: A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. An ultra-thin adhesion layer is applied to a degassed, pre-cleaned substrate. The degassed and pre-cleaned substrate is exposed to a precursor gas containing the adhesion layer, optionally deposited by a plasma-assisted CVD process, resulting in the deposition of an adhesion layer inside the exposed feature. The treated wafer is then coated with a diffusion barrier material, such as ruthenium, so that the adhesion layer reacts with incoming diffusion barrier atoms. The adhesion layer may be selectively bias-sputter etched prior to the deposition of the diffusion barrier layer. A copper layer is then deposited on the diffusion barrier layer.

Abstract: A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence of an alcohol. Also included in embodiments of the invention are materials with bonds healed by embodiments of the claimed method.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Abstract: The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film.

Abstract: A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected to the semiconductor chip, and pattern wirings connected to the via wirings. The method includes: forming the electrode layers, each having one or more through holes which the via wirings pierce, and the dielectric layer, and forming the capacitor; installing the capacitor such that the capacitor opposes the pattern wirings over an insulating layer; forming one or more via holes which reach the pattern wirings from the through holes; and forming the via wiring in the via hole.

Abstract: An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

Abstract: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.

Abstract: A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract: Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.

Abstract: There is provided a barrier structure provided with a concave portion corresponding to a pattern formed out of a functional liquid, the barrier structure comprising: a first concave portion provided in the barrier to correspond to a first pattern; and a second concave portion that is connected to the first pattern and is provided in the barrier to correspond to a second pattern having a width smaller than that of the first pattern, wherein the height of at least a part of the bottom surface of the second concave portion is greater than that of the bottom surface of the first concave portion.

Abstract: In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the upper surface of the conductive region to expose the upper surface of the conductive region. After the selectively removing process, at least a portion of the liner remains over the lower surface of the trench and the sidewalls of the trench and the via hole. A wet etch can then be performed to etch a recess in the conductive region. A conductive material is then formed within the damascene structure. This conductive material physically contacts the conductive region and is separated from the dielectric layer by the remaining portion of the liner.

Abstract: A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.

Abstract: A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first trench/via located in the first dielectric layer. A copper conductor fills the first trench/via. An electromigration inhibiting barrier layer is selectively located over a surface of the copper conductor and not any other remaining exposed surface. An insulating cap layer overlies the barrier layer and the remaining exposed surface. A second dielectric layer overlies the insulating cap layer. A second trench/via is located in the second dielectric layer and extends through the insulating cap layer and the barrier layer. A micro-trench is located within the first dielectric layer and is associated with the formation of the second trench/via. The micro-trench exposes a portion of the copper conductor. A filler fills the micro-trench.

Abstract: A method of forming a metal line, in which a nitride layer is used instead of a metal barrier layer, enabling a metal line structure with a relatively low resistance and therefore realizing a high integration of a device. In the method of forming the metal line of the semiconductor device, a first insulating layer and a second insulating layer with a different etch selectivity are sequentially formed on a semiconductor substrate. Predetermined regions of the first insulating layer and the second insulating layer are sequentially etched to form a contact hole. A metal barrier layer is formed on the entire surface including the contact hole. A first metal material is deposited on the entire surface to gap-fill the contact hole. The first metal material on the second insulating layer is stripped such that the first metal material remains only within the contact hole, thus forming a contact plug. A metal line is formed on a predetermined region of the second insulating layer including the contact plug.

Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

Abstract: Methods of manufacturing a semiconductor device having reduced susceptibility to void formation between upper metal wiring layers and lower contact pads are provided. According to the methods, an etch shield layer is formed to protect contact pads from subsequent etch processes. Semiconductor devices manufactured according to the methods are also provided.

Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.